Fast Reliable Verification Methodology for RISC-V Without a Reference Model

Munir, Abdelfattah; Magdy, Mina; Ahmed, Samer F.; Nasr, Sherouk; El-Ashry, Sameh; Shalaby, Ahmed

doi:10.1109/mtv.2018.00012

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…Up to now, there are plenty of RISC-V processors that have been presented in both academic and industrial forums. The IP cores, the System-on-Chips (SoCs), and the development kits were proposed and developed in both Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs) [9][10][11][12][13]. Some worthmention works are the highly customizable Rocket cores of the Berkeley architecture group [14], the high-performance 32-bit E-core series [15] and 64-bit U-core series [16] of IEICE Electronics Express, Vol.VV, No.NN, [1][2][3][4][5][6] the SiFive Inc., and the 32-bit RI5CY cores [17] and 64-bit Ariane cores [18] of the PULP-platform research group.…”

Section: Risc-v Is An Open-source Isa That Was First Presented By Thementioning

confidence: 99%

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Hoang

Duran

Nguyen

et al. 2020

IEICE Electron. Express

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In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm 2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V DD) with +1.6-V back-gate bias voltage (V BB). The best power density of 33.4-W/MHz is reached at 0.5-V V DD with +0.8-V V BB. The least current leakage of 3-nA is retrieved at 0.5-V V DD with −2.0-V V BB .

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