Fast subword permutation instructions using omega and flip network stages

Yang, Xiao; Lee, R.B.

doi:10.1109/iccd.2000.878264

Cited by 39 publications

(39 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is a significant result since previously arbitrary n-bit bit permutations took O(n) cycles. Even with our recent proposals of permutation instructions [5][9] [10][11] [12], this took at least O(log(n)) cycles. We show how a different 64-bit dynamically-specified permutation can be achieved every cycle by a 4-way superscalar processor with datarich MOMR execution.…”

Section: Discussionmentioning

confidence: 99%

“…Several approaches were proposed. The CROSS [9] and OMFLIP [10] permutation instructions each performs the equivalent function of two stages of a "virtual" interconnection network. A sequence of log(n) CROSS or OMFLIP instructions can build a 2log(n)-stage virtual network that can achieve any one of the n!…”

Section: Past Workmentioning

confidence: 99%

“…We then test DES using an enhanced ISA that has an OMFLIP permutation instruction [10] added to it (columns c and d). For multi-word operations, we test integer Diffie-Hellman (column e).…”

Section: Performancementioning

confidence: 99%

See 2 more Smart Citations

Validating Word-Oriented Processors for Bit and Multi-word Operations

Lee

Yang

Shi

2004

Advances in Computer Systems Architecture

View full text Add to dashboard Cite

Abstract. We examine secure computing paradigms to identify any new architectural challenges for future general-purpose processors. Some essential security functions can be provided by different classes of cryptography algorithms. We identify two categories of operations in these algorithms that are not common in previous general-purpose workloads: bit operations within a word and multi-word operations. Both challenge the basic word orientation of processors. We show how very complex bit-level operations, namely arbitrary bit permutations within a word, can be achieved in O(1) cycles, rather than O(n) cycles as in existing RISC processors. We describe two solutions: one using only microarchitecture changes, and another with Instruction Set Architecture (ISA) support. We generalize our solutions to define datarich execution with MOMR (Multi-word Operands Multi-word Result) functional units. This can address both challenges, leveraging available resources in typical processors with minimal additional cost. Thus we validate the basic word-orientation of processor architectures, since they can also provide superior performance for both bit and multi-word operations needed by cryptographic processing.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Past Workmentioning

confidence: 99%

See 1 more Smart Citation

Validating Word-Oriented Processors for Bit and Multi-word Operations

Lee

Yang

Shi

2004

Advances in Computer Systems Architecture

View full text Add to dashboard Cite

show abstract

“…In one method, individual bits of the source datum are selected and shifted to their destination locations using a series of logical AND, logical OR, and shift instructions [18]. For an arbitrary permutation of the bits in an n-bit word, this procedure requires as many as 4n instructions.…”

Section: Past Workmentioning

confidence: 99%

“…Lookup tables can also be employed to perform permutations with repetitions in software [18]. First, the n-bit source datum is divided into x groups of bits; each group is used to index a unique lookup table.…”

Section: Past Workmentioning

confidence: 99%

Architectural enhancements for fast subword permutations with repetitions in cryptographic applications

McGregor

Lee²

Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001

Self Cite

View full text Add to dashboard Cite

show abstract

Implementation of Izhikevich neuron based on stochastic computing using a novel inspired Omega‐Flip stochastic number generator

Hedayatpour

Karami

Shamsi

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

This paper presents an optimized stochastic multiplier to implement Izhikevich spiking neuron model. A novel stochastic number generator is used as the main block for stochastic computing to design a stochastic multiplier. The designed multiplier was used to describe and implement Izhikevich neuron model equation which is capable to produce variant responses of spiking neurons. To the best of the author's knowledge, this work is the pioneer using a designed multiplier for computing all of the multiplication expressions in spiking neuron equation. The effect of increasing number of bit streams on the accuracy of stochastic computing is studied. Furthermore, some numerical intervals that are more prone to the error are found and illustrated upon stochastic computing usage, and a method is proposed to improve the error prone numerical intervals. In addition, the response accuracy is optimized by changing time step parameter in solving ordinary differential Izhikevich neuron model equation using Euler's method. Hence, a 13‐bit stochastic multiplier is designed. It is found that variations in parameters a and b have a profound effect on the accuracy of recovery variable u and, consequently, on the responses. Out of 20 responses of Izhikevich neuron model, 11 responses are generated using the proposed stochastic computing method and compared with piecewise linear method and some previous architectures of Izhikevich neuron model implementations.

show abstract

Fast subword permutation instructions using omega and flip network stages

Cited by 39 publications

References 5 publications

Validating Word-Oriented Processors for Bit and Multi-word Operations

Validating Word-Oriented Processors for Bit and Multi-word Operations

Architectural enhancements for fast subword permutations with repetitions in cryptographic applications

Implementation of Izhikevich neuron based on stochastic computing using a novel inspired Omega‐Flip stochastic number generator

Contact Info

Product

Resources

About