Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes

Pullini,; Angiolini,; Bertozzi,; Benini, Luca

doi:10.1109/sbcci.2005.4286861

Cited by 21 publications

(9 citation statements)

References 17 publications

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“…Research has focused on complete architectures [10], flow control protocols [13], Quality of Service (QoS) provisions [7,20], support CAD tools [5], asynchronous implementations [6]. The flow towards a NoC layout has been explored in [14,1], a test chip is shown in [11], and an FPGA target is provided for [23].…”

Section: Related Workmentioning

confidence: 99%

Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness

Angiolini

Meloni

Carta

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementing efficient interconnect systems for devices which are ever more densely packed with parallel computing cores. Easily seen that traditional buses can not provide enough bandwidth, a revolutionary path to scalability is provided by packet-switched Network-on-Chips (NoCs), while a more conservative approach dictates the addition of bandwidth-rich components (e.g. crossbars) within the preexisting fabrics. While both alternatives have already been explored, a thorough contrastive analysis is still missing. In this paper, we bring crossbar and NoC designs to the chip layout level in order to highlight the respective strengths and weaknesses in terms of performance, area and power, keeping an eye on future scalability. 1

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Section: Related Workmentioning

confidence: 99%

Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness

Angiolini

Meloni

Carta

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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“…The xpipesLite switch relies on a stall/go flow control protocol [25]. It requires two control wires: one going forward and flagging data availability ("valid") and one going backward and signaling either a condition of buffer filled ("stall") or of buffer free ("go").…”

Section: A Baseline Vc-less Switchmentioning

confidence: 99%

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip

Gilabert

Gómez

Medardoni

et al. 2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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Virtual channels are an appealing flow control technique for on-chip interconnection networks (NoCs), in that they can potentially avoid deadlock and improve link utilization and network throughput. However, their use in the resource constrained multi-processor system-on-chip (MPSoC) domain is still controversial, due to their significant overhead in terms of area, power and cycle time degradation. This paper proposes a simple yet efficient approach to VC implementation, which results in more area- and power-saving solutions than conventional design techniques. While these latter replicate only buffering resources for each physical link, we replicate the entire switch and prove that our solution is counter intuitively more area/power efficient while potentially operating at higher speeds. This result builds on a well-known principle of logic synthesis for combinational circuits (the area-performance trade-off when inferring a logic function into a gate-level netlist), and proves that when a designer is aware of this, novel architecture design techniques can be conceived

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“…3D OASIS-NOC uses Stall-Go flow control as represented in Fig.9, which proves to be a low-overhead efficient design choice showing remarkable performance comparing to the other flow control schemes [16]. It communicates with the switch allocator module to give grant or send a stop signal to the source node to prevent from sending more flits to the destination node.…”

Section: Stall-go Flow Controlmentioning

confidence: 99%

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

Ahmed

Abdallah

Kuroda

2010

2010 International Conference on Broadband, Wireless Computing, Communication and Applications

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During this last decade, Network-on-Chips (NoC) have been proposed as a promising solution for future systems on chip design. It offers more scalability than the sharedbus based interconnection, allows more processors to operate concurrently. Because NoC has dedicated wires, performance can be predicted. In this context, we proposed a 2D-NoC named OASIS, which is a 4x4 mesh topology design using Wormhole switching and Stall-and-Go flow control scheme. Although OASIS-NoC has its advantages over the shared-bus based systems, it has also some limitations such as high power consumption, high cost communication, and low throughput.To overcome those limitations we propose a 3D-NoC (3D OASIS-NoC) which is an extension to our 2D OASIS-NoC. In this paper we describe the 3D OASIS-NoC architecture in a fair amount of detail and present preliminary evaluation results.

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Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes

Cited by 21 publications

References 17 publications

Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness

Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

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