FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics

Vitale, Steven A.; Wyatt, P.W.; Checka, Nisha; Kedzierski, J.; Keast, C.L.

doi:10.1109/jproc.2009.2034476

Cited by 91 publications

(42 citation statements)

References 29 publications

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“…This technology is specifically optimized for subthreshold operation by using an undoped channel to reduce capacitance and improve V T control [18]. In addition, the gate spacer is widened and the source/drain extensions are removed which has only a small impact on I ON due to low V DS barrier.…”

Section: Resultsmentioning

confidence: 99%

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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Abstract:The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write V MIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4][5][6][7][8][9][10][11][12][13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write V MIN by 100 mV over the unassisted test case.

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Section: Resultsmentioning

confidence: 99%

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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“…One particular structural innovation for better gate control is the move from bulk silicon substrates to silicon-on-insulator (SOI) substrates to avoid other short channel effects such as punch through leakage current 5,6,7,8 . IBM made the first 64 bit power microprocessor in 0.22um CMOS SOI technology in 1997 9 .…”

Section: Channel and Gate Engineeringmentioning

confidence: 99%

“…Performance improvement depends on the following factors (1) distance between S/D, (2) raised or embedded S/D growth, (3) epi growth profile, (4) S/D etch shape profile, (5) S/D etch depth, (6) volume of Ge material for PMOS, (7) fin pitch, (9) single fin vs multi-gated nested fins, (8) in-situ doping profile, (10) active dopant density, (11) lightly doped profile closer to the junction/channel interface to the heavily doped region near the silicide/contact interface, and (12) for alternate channel materials, the S/D epi should provide compressive strain to the PMOS channel and tensile strain to the NMOS channel.…”

Section: Challenges In Epitaxial Source and Drain Formationmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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“…Moreover, the and voltages tend to scale by same factor to limit drive-current degradation. Nevertheless, the SCE such as gate-induced drain leakage, gate oxide tunneling, drain-induced barrier lowering have a direct impact on the which has resulted in an exponential increase of the off-state leakage current [1][2][3]. Therefore, the most significant trend in bulk CMOS technology is the increasing contribution of leakage power in the total power dissipation of a bulk electronic designed system as shown in Fig.…”

Section: Downscaling Challenges In Bulk Technologymentioning

confidence: 99%

“…For instance, a modest leakage current around 100 nA per transistor, can cause a smartphone chip containing one hundred million transistors to consume a standby current of 10 A, thus, the battery would be drained in minutes without receiving or transmitting any signals. Therefore, new transistor architectures along with novel design methodologies that manage the low power circuits are required to boost green communication by taking advantage of the new energy-harvesting technology which recharge batteries by scavenging power from motion, wireless power transfer, and solar cells [3].…”

Section: Introductionmentioning

confidence: 99%

UTTB FDSOI Back-Gate Biasing for Low Power and High-Speed Chip Design

Dghais

Rodrı́guez

2015

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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Abstract. The paper presents the advantage of the Ultra-thin body and buriedoxide (BOX) (UTTB) fully depleted silicon-on-insulator (FDSOI) as an enabling transistor technology through effective back-gate biasing schemes to overcome the challenges that arises from downscaling bulk CMOS technology for low power and high-speed design tradeoff. The effects of the back-gate bias methodologies that can vary or modulate the substrate bias to adapt the transistor's threshold voltage are detailed. The design schemes that can be used with this technology are described to illustrate their applications with UTTB FDSOI transistor.

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FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics

Abstract: Silicon-on-insulator devices designed for optimum operation at 0.3 V promise longer operational life than conventional application-specific integrated circuits.

Cited by 91 publications

References 29 publications

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Scaling Challenges for Advanced CMOS Devices

UTTB FDSOI Back-Gate Biasing for Low Power and High-Speed Chip Design

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