Finding All Attractive Train Connections by Multi-criteria Pareto Search

Müller‐Hannemann, Matthias; Schnee, Mathias

doi:10.1007/978-3-540-74247-0_13

Cited by 48 publications

(30 citation statements)

References 12 publications

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“…This will hold especially true for algorithms working on large data sets (such as for railway routing graphs [41]) that easily exceed the cache capacities of modern processors, also reducing them to the raw speed of the main memory system. Modern reconfigurable devices are already reaching these speeds, but beyond that can then exploit increased parallelism, with regard to both number of memory banks and processing elements.…”

Section: Discussionmentioning

confidence: 99%

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Lange

Koch

2010

IEEE Trans. Comput.

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Abstract-We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23x times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89% of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility / performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.

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Section: Discussionmentioning

confidence: 99%

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Lange

Koch

2010

IEEE Trans. Comput.

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“…One speed advantage of modern CPUs is often due to the tight integration of fast multi-megabyte caches within the processor, something generally not possible with commercially available RDs. However, the moment the size of irregular data sets exceeds the cache size (such as for railway routing graphs [21]), CPU performance drops to the speed of the memory system. Modern RDs are already reaching these speeds, but beyond that can then exploit increased parallelism, both with regard to number of memory banks and processing elements.…”

Section: Discussionmentioning

confidence: 99%

An Execution Model for Hardware/Software Compilation and its System-Level Realization

Lange

Koch

2007

2007 International Conference on Field Programmable Logic and Applications

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We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then characterize the architectural and OS-level requirements of implementing the model, and demonstrate how they can be achieved on a real hardware platform running under a full scale multi-tasking virtual protected memory operating system. Experimental measurements show the efficiency of our solution, and also prove that reconfigurable computing can be competitive with processors even for nonstreaming, pointer-chasing applications.

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“…For example, users traveling by train may be willing to accept longer travel times if the number of required transfers is lower or the cost of a journey with longer duration is cheaper. We end up in a multi-criteria scenario [53,57,21] in which none of the high-performance approaches developed in the last years can be applied easily. The adaption of a fast method to this scenario is one of the main challenges in the near future.…”

Section: Dynamizationmentioning

confidence: 99%

“…Although the resulting graphs are time-independent, the main downside of this approach is the increase in input size. While this is still practicable for timetable information [53,30], the time-expanded graphs get way too big for road networks. In addition, adaption of speedup techniques to the time-expanded approach is more complicated than expected [9].…”

Section: Modeling Issuesmentioning

confidence: 99%

Engineering Route Planning Algorithms

Delling

Sanders

Schultes

et al. 2009

Lecture Notes in Computer Science

370

235

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Abstract. Algorithms for route planning in transportation networks have recently undergone a rapid development, leading to methods that are up to three million times faster than Dijkstra's algorithm. We give an overview of the techniques enabling this development and point out frontiers of ongoing research on more challenging variants of the problem that include dynamically changing networks, time-dependent routing, and flexible objective functions.

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Finding All Attractive Train Connections by Multi-criteria Pareto Search

Cited by 48 publications

References 12 publications

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

An Execution Model for Hardware/Software Compilation and its System-Level Realization

Engineering Route Planning Algorithms

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