Finite-Element Analysis of Semiconductor Devices: The FIELDAY Program

Buturla, E. M.; Cottrell, P.E.; Grossman, B.M.; Salsburg, K. A.

doi:10.1147/rd.254.0218

Cited by 285 publications

(44 citation statements)

References 35 publications

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“…However, the conclusions do not depend on this choice, since other extraction methods were shown to produce similar values of . Process and device simulations were done using a modified version of TSuprem-4 [14] and FIELDAY [15], respectively. Table I also compares the matching of simulation results and measured device parameter values for four process model assumptions.…”

Section: Simulation Resultsmentioning

confidence: 99%

A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

Young

Ieong

et al. 1998

IEEE Electron Device Lett.

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A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. Dopant in the source-drain extension is assumed to segregate to the Si/SiO 2 interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail.

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Section: Simulation Resultsmentioning

confidence: 99%

A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

Young

Ieong

et al. 1998

IEEE Electron Device Lett.

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“…In contrast to most other semiconductor modeling software, it solves the equations not with the finite-difference but with a finite-element method [33]. This method is well suited for one dimensional semiconductors (but in 2D only under special circumstances [34], and in 3D it requires special basis functions [35]). For a comparison between the two approaches, see [36].…”

Section: Developments From a Historical Perspectivementioning

confidence: 99%

Models for numerical device simulations of crystalline silicon solar cells—a review

2011

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Current issues of numerical modeling of crystalline silicon solar cells are reviewed. Numerical modeling has been applied to Si solar cells since the early days of computer modeling and has recently become widely used in the photovoltaics (PV) industry. Simulations are used to analyze fabricated cells and to predict effects due to device changes. Hence, they may accelerate cell optimization and provide quantitative data e.g. of potentially possible improvements, which may form a base for the decision making on development strategies. However, to achieve sufficiently high prediction capabilities, several models had to be refined specifically to PV demands, such as the intrinsic carrier density, minority carrier mobility, recombination at passivated surfaces, and optical models. Currently, the most unresolved issue is the modeling of the emitter layer on textured surfaces, the hole minority carrier mobility, Auger recombination at low dopant densities and intermediate injection levels, and fine-tuned band parameters as a function of temperature. Also, it is recommended that the widely used software in the PV community, PC1D should be extended to FermiDirac statistics.

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“…Each decoupled equation is solved with the adaptive finite volume and the monotone iterative methods [6]. Domain discretization is with a Delaunay triangulation meshing technique, which generates polyhedron over the 3D device structure [10,11]. In setting the device parameters for our 3D device simulation, the device gate length is fixed at 25 nm for both the bulk and SOI FinFETs on substrates with [100] orientation.…”

Section: Computational Modelmentioning

confidence: 99%

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

2006

J Comput Electron

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In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I D -V G and I D -V D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.

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Finite-Element Analysis of Semiconductor Devices: The FIELDAY Program

Cited by 285 publications

References 35 publications

A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

Models for numerical device simulations of crystalline silicon solar cells—a review

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

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