Formal verification of safety properties in timed circuits

Abstract

The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed state space, a conservative overestimation that fulfills the property under verification is derived. Timing analysis with absolute delays is efficiently performed at the level of event structures and transformed into a set of relative timing constraints. With this approach, conventional symbolic techniques for reachability analysis can be efficiently combined with timing analysis. Moreover, the set of timing constraints used to prove the correctness of the circuit can also be reported for backannotation purposes. Some preliminary results obtained by a naive implementation of the approach show that systems with more than ½¼ untimed states can be verified. £ This work has been partially funded by a grant from Intel Corporation, ACiD-WG (ESPRIT 21949), and the Ministry of Education of Spain under contracts CICYTs TIC 98-0410 and TIC 98-0949.

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

“…Table 1 compares our new gate-level timing verification method using standard benchmarks against results for the timed automata tool KRONOS [9], a conservative approximation method described in [14], and the ATACS explicit state timing verifier [12]. For KRONOS runtimes, an entry with a question mark indicates the amount of time after which the verification ran out of memory.…”

“…This verification must be extremely efficient to allow for many alternative designs to be considered during technology mapping. Current timing verification algorithms [13,3,14,10,9,18] often suffer from state explosion problems because each node in the circuit netlist is treated as a new state variable, potentially doubling the number of states.…”

A proposal for relative time Petri nets

“…Other work on incorporating relative time into reachability analysis has been carried out particularly in the area of asynchronus circuit design [3,9]. The construction of lazy transition systems is used during synthesis to prune a previously explored untimed state space of those areas which cannot be reached due to the timing constraints of the system.…”

Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip

“…Compared to timed methods, such as [5] and [10], metric-free verification is less computationally-intensive and integrates more easily within a hierarchical verification framework that permits non-determinism. Metric-free verification methods for relative timing are also used in [17].…”