2012 International Conference on Devices, Circuits and Systems (ICDCS) 2012
DOI: 10.1109/icdcsyst.2012.6188780
|View full text |Cite
|
Sign up to set email alerts
|

Four BIT CMOS full adder in submicron technology with low leakage and Ground bounce noise reduction

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2013
2013
2018
2018

Publication Types

Select...
3
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(1 citation statement)
references
References 7 publications
0
1
0
Order By: Relevance
“…Leakage power has become critical issue [4], because electronic devices such as mobile phones, laptops, and other battery operated devices remain in standby mode for most of the time, which results in sharp battery discharge due to heavy leakage current [5]. Several techniques have been used in the past for reduction in leakage power in digital circuits but most commonly used technique is power gating [6]. It uses sleep transistors which provide high impedance between Vdd and GND during sleep mode to reduce leakage power.…”
Section: Introductionmentioning
confidence: 99%
“…Leakage power has become critical issue [4], because electronic devices such as mobile phones, laptops, and other battery operated devices remain in standby mode for most of the time, which results in sharp battery discharge due to heavy leakage current [5]. Several techniques have been used in the past for reduction in leakage power in digital circuits but most commonly used technique is power gating [6]. It uses sleep transistors which provide high impedance between Vdd and GND during sleep mode to reduce leakage power.…”
Section: Introductionmentioning
confidence: 99%