2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) 2013
DOI: 10.1109/i2mtc.2013.6555696
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FPGA based architectures for high performance adaptive FIR filter systems

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Cited by 6 publications
(18 citation statements)
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“…A direct implementation of these operations in the hardware involves large amount of resources and higher latency. To overcome these, many methods are discussed in the literature which approximates these functions using LUT based log domain arithmetic [2,3,7], LUT based Newton-Raphson [4,5], CORDIC based architectures [9], and so forth. In [8], the square root operation is approximated using CORDIC and inverse square root is done by division.…”
Section: Background and Related Workmentioning
confidence: 99%
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“…A direct implementation of these operations in the hardware involves large amount of resources and higher latency. To overcome these, many methods are discussed in the literature which approximates these functions using LUT based log domain arithmetic [2,3,7], LUT based Newton-Raphson [4,5], CORDIC based architectures [9], and so forth. In [8], the square root operation is approximated using CORDIC and inverse square root is done by division.…”
Section: Background and Related Workmentioning
confidence: 99%
“…a modified boundary cell (from [4,5]) is proposed (Figure 1(c)) which computes the square root utilizing the same LUT and NR blocks (square root is computed by delaying the input value sufficiently and then multiplying it with its inverse square root value obtained from NR logic), thus reducing the resource utilization. LUT-N method consists of a control logic, LUT blocks, and NR iteration equation.…”
Section: Boundary Cellmentioning
confidence: 99%
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