FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System

Sobaihi, Khaled; Hammoudeh, Akram; Scammell, David

doi:10.1109/reconfig.2010.40

Cited by 9 publications

(8 citation statements)

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“…There are many FPGA implementations of OFDM modems and also many related publications, [4][5][6][7][8][9][10][11][12][13]. Xilinx FPGA boards are widely used in these publications.…”

Section: State Of the Artmentioning

confidence: 99%

Towards Multi-gigabit OFDM Throughput on FPGA: Limitations and Challenges

Dokoski¹,

Tentov²

2014

Lecture Notes in Electrical Engineering

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This paper explores the possibility of achieving multi-gigabit data throughput over wireless networks, by using the FPGA technology. It focuses on the implementation complexity of an Orthogonal Frequency-Division Multiplexing (OFDM) modulation, as the most complex part of a physical layer in an 802.11 wireless network.The calculations are performed for a typical OFDM system, as synthesized in the Xilinx ISE Studio for the most popular Xilinx FPGA architectures. The results present the upper processing speeds that can be expected from an FPGA implementation of an OFDM modem.

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“…There are many FPGA implementations of OFDM modems and also many related publications, [4][5][6][7][8][9][10][11][12][13]. Xilinx FPGA boards are widely used in these publications.…”

Section: State Of the Artmentioning

confidence: 99%

Towards Multi-gigabit OFDM Throughput on FPGA: Limitations and Challenges

Dokoski¹,

Tentov²

2014

Lecture Notes in Electrical Engineering

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“…Since the decomposition of the DFT is not unique, it is natural to ask how to manage splitting and how to obtain the fastest algorithm of the DFT. The difference between the lower bound of arithmetical operations and the complexity of fast transform algorithms shows that it is possible to obtain FFT algorithms of various speed [2]. One approach is to design efficient manageable split algorithms.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The signal/image processing related to engineering research becomes increasingly dependent on the development and implementation of the algorithms of orthogonal or non-orthogonal transforms and convolution operations in modern computer systems. The increasing importance of processing large vectors and parallel computing in many scientific and engineering applications require new ideas for designing super-efficient algorithms of the transforms and their implementations [2].The hardware implementation of FFT approaches is a challenging issue where the digital signal processors (DSPs) and the field programmable gate array (FPGA) chips are two considering designing environments for implementing different schemes of FFT approaches.Recently, the FPGA technology [3] is quit mature for digital signal processing applications [4] due to fast progress in very large scale integration (VLSI) technology. The FPGA devices provide fully programmable system-on-chip environments by incorporating the programmability of programmable logic devices and the architecture of gate arrays.…”

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confidence: 99%

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Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

Singhal¹,

Goen²,

Mohapatrara³

2018

IJERMT

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Abstract:he Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware's like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs by developing our own FFT processor architecture. Keywords I. INTRODUCTIONIn the recent decades DFT has been playing several important roles in advanced applications such as image compression and reconstruction in biomedical images, audiology research for analyzing biomedical brain-stem speech signals, sound filtering, data compression, partial differential equations, and multiplication of large integers.The fast algorithms for DFT always look for DFT process to be fast, accurate and simple. Fast is the most important [5]. Since the introduction of the Fast Fourier Transform (FFT), Fourier analysis has become one of the most frequently used tool in signal/image processing and communication systems; The main problem when calculating the transform relates to construction of the decomposition, namely, the transition to the short DFT's with minimal computational complexity. The computation of unitary transforms is complicated and time consuming process. Since the decomposition of the DFT is not unique, it is natural to ask how to manage splitting and how to obtain the fastest algorithm of the DFT. The difference between the lower bound of arithmetical operations and the complexity of fast transform algorithms shows that it is possible to obtain FFT algorithms of various speed [2]. One approach is to design efficient manageable split algorithms. Indeed, many algorithms make different assumptions about the transform length [5]. The signal/image processing related to engineering research becomes increasingly dependent on the development and implementation of the algorithms of orthogonal or non-orthogonal transforms and convolution operations in modern computer systems. The increasing importance of processing large vectors and parallel computing in many scientific and engineering applications require new ideas for designing super-efficient algorithms of the transforms and their implementations [2].The hardware implementation of FFT approaches is a challenging issue where the digital signal processors (DSPs) and the field programmable gate array (FPGA) chips are two considering designing environments for implementing different schemes of FFT approaches.Recently, the FPGA techn...

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“…Often critical components such as synchronization and tracking loops needed to have a working demonstrator are omitted or postponed for later studies [3]. Further, in some cases, evaluations are limited to simulations or are done in isolation without considering the impact of the RF front-end which can impose significant nonlinearities on the signal (e.g.…”

Section: Introductionmentioning

confidence: 99%

Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation

Guntur

Jansen

Hoogerbrugge

et al. 2013

2013 23rd International Conference on Field Programmable Logic and Applications

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This paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. The baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. The demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beamforming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using π/2 QPSK modulation with a 13/16 LDPC code rate.

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FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System

Cited by 9 publications

References 10 publications

Towards Multi-gigabit OFDM Throughput on FPGA: Limitations and Challenges

Towards Multi-gigabit OFDM Throughput on FPGA: Limitations and Challenges

Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation

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