Fracture mechanics based crack and delamination risk evaluation and RSM/DOE concepts for advanced microelectronics applications

Auersperg, J.; Seiler, B.; Cadalen, Eric; Dudek, R.; Michel, B.

doi:10.1109/esime.2005.1502799

Cited by 17 publications

(8 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Bulk and bimaterial fracture mechanics approaches establish a good basis for evaluating cracking processes and optimization towards higher reliability and robust design [4,14] but, it is to be noted that • some of the approaches are restricted to LEFM (SIF, mode separation for VCCT [5][6][7]), • some have to be checked for path independence of the results (J-or M-integrals) and some seem less applicable for unloading situations (J-integral, VCCT, ARE [13] etc.). Although CZM [8][9][10][11] and XFEM [12] have the potential of incorporating micromechanical conditions and processes, they show also some difficulties -mesh dependence, time integration instability and the huge number of model-parameters that have to be measured prior to the simulations.…”

Section: Multiple Failure Evaluation In Beolmentioning

confidence: 99%

Crack and damage in low-k BEoL stacks under assembly and CPI aspects

Auersperg

Vogel

Lehr

et al. 2010

2010 11th International Thermal, Mechanical &Amp; Multi-Physics Simulation, and Experiments in Microelectronics and Microsystem

Self Cite

View full text Add to dashboard Cite

Miniaturization and increasing functional integration as the electronic industry drives push the development of feature sizes down to the nanometer range. Moreover, harsh operational conditions and new porous or nano-particle filled materials introduced on both chip and package level - low-k and ultra low-k materials in Back-end of line (BEoL) layers of advanced CMOS technologies, in particular - cause new challenges for reliability analysis and prediction. The authors show a combined numerical/experimental approach and results towards optimized fracture and fatigue resistance of those BEoL structures under manufacturing/packaging (during lead-free reflow-soldering, in particular) as well as chip package interaction (CPI) aspects by making use of bulk and interface fracture concepts, in multi-scale and multi-failure modeling approaches with several kinds of failure/fatigue phenomena. Probable crack paths and interactions between material damaging and interface fracture will be investigated and sensitivities with regard to structural modifications studied. Complementary to the simulation side of reliability estimations, serious issues are connected with the collection of appropriate material properties in the miniaturized range addressed - Young's modulus initial yield stress, hardening. Nano-indentation, AFM, FIB and EBSD provide these desired properties, in particular. In addition, manufacturing induced residual stresses in the Back-end layer stack have an essential impact on damage behavior, because they superpose functional and CPI loads. Their determination with a spatial resolution necessary for typical BEoL structure sizes is a critical issue. The nano-scale stress relief technique (fibDAC) makes use of tiny trenches placed with a focused ion beam (FIB) equipment at the position of stress measurement. Digital image correlation algorithms applied to SEM micrographs captured before and after ion milling allows to conclude on stresses released. Residual stress

show abstract

Section: Multiple Failure Evaluation In Beolmentioning

confidence: 99%

Crack and damage in low-k BEoL stacks under assembly and CPI aspects

Auersperg

Vogel

Lehr

et al. 2010

2010 11th International Thermal, Mechanical &Amp; Multi-Physics Simulation, and Experiments in Microelectronics and Microsystem

Self Cite

View full text Add to dashboard Cite

show abstract

“…Figure 1 shows the FE-model of a quarter of an underfilled FC with circumferential bumps and single middlbump. As discussed in [16], varying the geometry of the finite element model accounted for keeping the finite elements regular (positive Jacobian) and to avoid element warpage and element distortion.…”

Section: Modeling Assumptionsmentioning

confidence: 99%

“…The application of an appropriate DOE-Software like LMS OPTIMUS™ [15] enables herewith to evaluate the influence of model parameters on the thermo-mechanical reliability, to optimize the design and the materials selection, to safe the reliability and also the robustness of found optimal solutions [16].…”

Section: Figure 9: Dependence Of Accumulated Equivalent Creep Strainsmentioning

confidence: 99%

Combined Fracture, Delamination Risk and Fatigue Evaluation of Advanced Microelectronics Applications towards RSM/DOE Concepts

Auersperg

Dudek

Michel

2006

EuroSime 2006 - 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electr

Self Cite

View full text Add to dashboard Cite

Microelectronic assemblies are basically compounds of several high precision materials with quite different Young's moduli and thermal expansion coefficients (CTE). Additionally, various kinds of inhomogeneity, residual stresses generated by several steps of the manufacturing process and extreme thermal environmental conditions contribute to interface delamination, chip cracking and fatigue of solder interconnects.For that reason, numerical investigations by means of nonlinear FEA together with conventional strength hypotheses are frequently used for design optimizations and sensitivity analyses. So, design studies on the basis of parameterized FE-models and DOE/RSM-approaches help to optimize electronic components at early phases of the product development process. But, this methodology typically bases on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches, whereas delamination or bulk fracture mechanisms usually remain unconsidered.By means of a representative microelectronics assembly this contribution is going to figure out and discuss ways and challenges of using numerical fatigue evaluation and fracture mechanics approaches in connection with parameterized finite element modeling based DOE/RSM-concepts. That is, the evaluation of mixed mode interface delamination phenomena utilizing the VCCT-methodology, classical strength hypotheses along with fracture mechanics approaches and modified Coffin-Manson thermal fatigue estimation of solder joints will be simultaneously applied within a multi-objective optimization towards a thermo-mechanical reliable design.

show abstract

“…The related characterization is bound to load mode mix observations, and methods have been suggested and used to extract mixed mode properties over a notable span of angles, e.g. [2,4,10]. Despite recent efforts for improvement [12] certain challenges remain.…”

Section: Introductionmentioning

confidence: 99%

Induced delamination of silicon-molding compound interfaces

Schlottig

Pape

Wunderle

et al. 2009

EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelect

View full text Add to dashboard Cite

Interface fracture properties are increasingly requested in electronic packaging, be it for design problems or reliability issues. We demonstrate an induced delamination of the epoxy molding compound and die silicon interface, and propose a mixed modechisel testing setup (MMC) and its experimental procedure. The MMC addresses several drawbacks of existing methods. The work includes samples from package fabrication processes and the establishing of critical fracture mechanics properties through finite element simulation. The setup allows for the investigation of interfaces at package scale

show abstract

Fracture mechanics based crack and delamination risk evaluation and RSM/DOE concepts for advanced microelectronics applications

Cited by 17 publications

References 8 publications

Crack and damage in low-k BEoL stacks under assembly and CPI aspects

Crack and damage in low-k BEoL stacks under assembly and CPI aspects

Combined Fracture, Delamination Risk and Fatigue Evaluation of Advanced Microelectronics Applications towards RSM/DOE Concepts

Induced delamination of silicon-molding compound interfaces

Contact Info

Product

Resources

About