From MARTE to Reconfigurable NoCs

Quadri, Imran Rafiq; Elhaji, Majdi; Meftali, Samy; Dekeyser, Jean-Luc

doi:10.4018/978-1-61520-807-4.ch006

Cited by 3 publications

(1 citation statement)

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“…Several topologies have been modeled in MARTE profile such as hypercube, star and ring [42]. In this paper we will divide the work into two parts.…”

Section: Methodology Flowmentioning

confidence: 99%

System level modeling methodology of NoC design from UML-MARTE to VHDL

Elhaji

Boulet²,

Zitouni³

et al. 2012

Des Autom Embed Syst

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The evolution of the semiconductor technology caters for the increase in the System-on-Chip (SoC) complexity. In particular, this complexity appears in the communication infrastructures like the Network-on-Chips (NoCs). However many complex SoCs are becoming increasingly hard to manage. In fact, the design space, which represents all the concepts that need to be explored during the SoC design, is becoming dramatically large and difficult to explore. In addition, the manipulation of SoCs at low levels, like the Register Transfer Level (RTL), is based on manual approaches. This has resulted in the increase of both time-to-market and the development costs. Thus, there is a need for developing some automated high level modeling environments for computer aided design in order to handle the design complexity and meet tight time-to-market requirements. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) allows the modeling of repetitive structures such as the NoC topologies which are based on specific concepts. This paper presents a new methodology for modeling concepts of NoC-based architectures, especially the modeling of topology of the interconnections with the help of the repetitive structure modeling (RSM) package of MARTE profile. This work deals with the ways of improving the effectiveness of the MARTE standard by clarifying and extending some notations in order to model complex NoC topologies. Our contribution includes a description of how these concepts may be mapped into VHDL. The generated code has been successfully evaluated and validated for several NoC topologies.

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“…Several topologies have been modeled in MARTE profile such as hypercube, star and ring [42]. In this paper we will divide the work into two parts.…”

Section: Methodology Flowmentioning

confidence: 99%