From TLM to FPGA: rapid prototyping with systemc and transaction level modeling

Klingauf, Wolfgang; Günzel, Robert

doi:10.1109/fpt.2005.1568563

Cited by 14 publications

(8 citation statements)

References 4 publications

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“…Methods for automated communication refinement from TLM to pin-and cycle-accurate protocols have been presented in [5][6][7]. In [6], abstract point-to-point First In, First Out (FIFO) channels are refined into a bus-based communication protocol.…”

Section: Related Workmentioning

confidence: 99%

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Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology

Moss

Cantin

Bois

et al. 2008

2008 the 19th IEEE/IFIP International Symposium on Rapid System Prototyping

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Traditionalregister-transfer level design methodologies for systems-on-chip are failing to keep up with the growing complexity of embedded applications and architectures. A well-known solution is to raise the level of design abstraction by using system-level methodologies. The refinement from system-level specifications to concrete implementations is an essential step in a system-level design methodology. This article presents a novel methodology for the refinement from transaction-level communications to pin-and cycleaccurate protocols as well as the generation of synthesizable hardware from system-level specifications. Automatic communication refinement and hardware synthesis were successfully applied to a rover guiding system. Hand-coded and automatically generated register-transfer level modules of the rover are compared. Results show that a hardware/software implementation of the guiding system using generated register-transfer level modules has overheads of less than one percent in latency and hardware area when compared to an implementation using hand-coded modules.

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Section: Related Workmentioning

confidence: 99%

“…In [6], abstract point-to-point First In, First Out (FIFO) channels are refined into a bus-based communication protocol. The application designer must write functions that marshall and unmarshall transferred abstract C/C++ data types into bit-accurate representations that are streamed on the bus.…”

Section: Related Workmentioning

confidence: 99%

Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology

Moss

Cantin

Bois

et al. 2008

2008 the 19th IEEE/IFIP International Symposium on Rapid System Prototyping

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show abstract

“…However, they deal with this at a very high level of abstraction supporting packet based communication only and therefore lack the possibility of providing cycle count accurate timing estimations. Other research groups identified the need of generic bus models but do not offer solutions [4,7].…”

Section: Related Workmentioning

confidence: 99%

GreenBus

Klingauf

Günzel

Bringmann

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have analysed, which are common in todays system on chip environments, and require to be modelled at a transaction level. Second our findings in terms of the data structures and interface API's that are required in order to model those (and we believe other) busses and IO structures. Third the surrounding infrastructure that we believe can, and should be in place to support the modelling of those busses and IO structures. We will present the infrastructure that we have built, and indicate where our future work will head.

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“…The OSCI TLM standard [12,9] seems well adapted for the modelling of communication in SystemC. There have already been some attempts to use TLM in rapid prototyping [7], which are promising. Commercial C/C++ to hardware tools like [1,8] allow behaviour level synthesis and gain more and more interest by the industry.…”

Section: Introductionmentioning

confidence: 99%

SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder

Grüttner¹,

Oppenheimer²,

Nebel³

et al. 2008

2008 Design, Automation and Test in Europe

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This paper will exemplarily describe and evaluate the OSSS methodology for embedded hardware/software systems and its use in a JPEG 2000 decoder case-study. The OSSS approach defines a design flow starting from an Application Model providing a rich subset of SystemC TM /C++ augmented with specific OSSS language concepts. It can be used to identify the most promising parallel structure by comparing different design alternatives. A clearly defined refinement process leads to the Virtual Target Architecture (VTA) Model. These refinements enable an analysis of the system behaviour at cycle-accurate granularity and support the exploration of different target architectures for the JPEG 2000 decoder. VTA models can be used as direct input for the FOSSY synthesis tool, which performs an automatic transformation into implementation models; that is to generate VHDL code for hardware, C/C++ for software, and platform configuration files for the target technology.

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From TLM to FPGA: rapid prototyping with systemc and transaction level modeling

Cited by 14 publications

References 4 publications

Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology

Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology

GreenBus

SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder

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