2018
DOI: 10.1088/1361-6641/aaa7a6
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Fully patterned p-channel SnO TFTs using transparent Al2O3 gate insulator and ITO as source and drain contacts

Abstract: SnO p-type was used as active layer to fabricate thin film transistors (TFTs) through photolithography and dry etching processes. The SnO p-type thin films (25 nm) were deposited by DC reactive sputtering with variable oxygen (O 2 ) flow rate to then be annealed in air at 250• C. Al 2 O 3 gate dielectric (15 nm) was deposited by atomic layer deposition. Hall measurements showed p-type carrier concentration (N h ) of around 1×10 18 cm −3 and Hall mobilities (μ Hall ) between 0.35 and 2.64 cm 2 V −1 s −1 , dep… Show more

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Cited by 16 publications
(7 citation statements)
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“…A high hole concentration (nh) of × cm -3 is obtained in the untreated SnO film, with a resistivity (ρ) of 0.5 Ω·cm and a Hall mobility (μHall) of 1 cm 2 /Vs. These are comparable to those reported in the literature [8][9]. When the fluorination treatment time increased from 0 s to 60 s, nh significantly decreased to .…”
Section: Resultssupporting
confidence: 91%
“…A high hole concentration (nh) of × cm -3 is obtained in the untreated SnO film, with a resistivity (ρ) of 0.5 Ω·cm and a Hall mobility (μHall) of 1 cm 2 /Vs. These are comparable to those reported in the literature [8][9]. When the fluorination treatment time increased from 0 s to 60 s, nh significantly decreased to .…”
Section: Resultssupporting
confidence: 91%
“…Furthermore, the improved electrical performance of ZnO TFT device is expected owing to the lower density of interface state ( D IT ) between the ZnO active layer and hybrid gate dielectric. Based on the SS and other electrical parameters, the D IT can be evaluated with the following equation: where q is the electron charge, k is the Boltzmann’s constant, e is the Euler’s number, T is the absolute temperature, and C ox is the capacitance per unit area (1.06 × 10 –7 F/cm 2 ) of the hybrid gate dielectric layer. Using eq , the density of interface state ( D IT ) of ZnO TFT device was estimated to be 3.46 × 10 12 cm –2 eV –1 .…”
Section: Results and Discussionmentioning
confidence: 99%
“…Furthermore, the improved electrical performance of ZnO TFT device is expected owing to the lower density of interface state (D IT ) between the ZnO active layer and hybrid gate dielectric. Based on the SS and other electrical parameters, the D IT can be evaluated with the following equation:41…”
mentioning
confidence: 99%
“…The wave-function overlapping of the symmetrical Sn 5s orbital near the top of VB provides an effective pathway for hole carrier transports in the SnO material. Besides, SnO has a reasonable hole dopability where the Sn vacancy (V Sn ) acting as an acceptor is easily created due to its relatively low formation energy . So far, various deposition methods have been used to prepare semiconducting p-type SnO thin films such as pulsed laser deposition, , electron beam evaporation, , solution process, reactive sputtering, atomic-layer-deposition, and thermal evaporation. The phase-stability map of β-Sn, SnO, and SnO 2 in the sputtered SnO system depending on the oxygen partial pressure and chamber pressure was constructed through hundreds of experiments . The mixed-phase SnO film with the approximately 3 atom % β-Sn second phase allowed the high hole mobility, attributable to the enhancement in the metallic character near the top of the valance band by the Sn interstitial.…”
Section: Introductionmentioning
confidence: 99%