Functional test pattern generation for asynchronous circuits

Abstract

Various approaches for functional test generation have been discussed and proposed in the past decade. The most significant difference lies in the circuit modeling methodologies, such as BDD, RTLs, HDLs, state transition diagram. In this paper, we develop a functional test generation algorithm, which generates test patterns directly from a grapbical model, called the signal transition graph (STG). STG has been widely used for the design and modeling of asynchronous circuits, so we focus on the test generation for asynchronous circuits. In addition, we propose a token propagation fault model to model the fault effects exhibiting on STG, and apply the equivalence/dominance fault collapsing analysis to reduce the number of faults to be considered.

ESD protection for slew-rate-controlled output buffer in a 0.5μm CMOS SRAM technology

“…may cause the gate-oxide rupture on the MN3 device. An ecient VDD-to-VSS ESD clamp circuit has to be added between the VDD and VSS power lines in the whole-chip ESD protection design [39,40].…”