Fundamental Interconnection Issues

Hornak, L.A.; Little, Trevor E.; Tewksbury, Stuart K.; Franzon, Paul D.

doi:10.1002/j.1538-7305.1987.tb00215.x

Cited by 24 publications

(8 citation statements)

References 38 publications

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“…In general, since interconnect lines are modeled as distributed transmission lines, their mathematical formulation results in the Telegrapher's equation. If the excitation signal is not sinusoidal but a general function, a transmission line response is presented in terms of space and time derivatives (1) (2)…”

Section: Interconnect Model Fundamentalsmentioning

confidence: 99%

“…In such circuits, interconnect lines become one of the crucial design issues for both signal delay and crosstalk because it is necessary to guarantee the signal integrity at the design stage. As technologies advance, their importance will be more apparent because the dominant signal distortions and logic failures will not be due to gates but due to the interconnect lines [1], [2]. In the complicated multilayered interconnect system, signal coupling and delay strongly affect circuit performance.…”

Section: Introductionmentioning

confidence: 99%

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A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

Eisenstadt

Jeong

et al. 2000

IEEE Trans. Electron Devices

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A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-m CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. Thereby, this model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design.

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Section: Interconnect Model Fundamentalsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

Eisenstadt

Jeong

et al. 2000

IEEE Trans. Electron Devices

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“…6(B)], the clock skew is defined as being negative. Negative clock skew can be used to improve the maximum performance of a synchronous system by decreasing the delay of a critical path; however, a potential minimum constraint can occur, creating a race condition [11], [12], [31], [138], [139], [145], [176], [179], [181]. In this case, when lags , the clock skew must be less than the time required for the data signal to leave the initial register, propagate through the interconnect, combinatorial logic, and setup in the final register (see Fig.…”

Section: B Minimum Data Path/clock Skew Constraint Relationshipmentioning

confidence: 99%

Clock distribution networks in synchronous digital integrated circuits

2001

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Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described, the clock distribution networks of specific industrial circuits are surveyed, and future trends are discussed.

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“…In the CMOS inverter circuit as shown in Fig. 1 (without taking the inductance into account), the CMOS inverter fall time can be decomposed of (1) where the first term represents time slot of the linear region and the second term represents the time of the saturation region of the CMOS inverter, i.e., If the saturation duration is long, the maximum current peak of NMOS transistor occurs at the end of the saturation period of the device operation. The , the saturation time components of the fall time, can be approximated by using the output current model of an NMOS transistor.…”

Section: A Saturation Time Of Nmos Transistormentioning

confidence: 99%

New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design

Eisenstadt

Jeong

et al. 2000

IEEE Trans. Adv. Packag.

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A new simple but accurate simultaneous-switchingnoise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed. Since the model is based on the sub-micron metal-oxide-semiconductor (MOS) device model, it can fairly well predict the SSN for today's sub-micron-based very large scale integration (VLSI) circuits. In order to derive the SSN model, the ground path current is determined by taking into account all the circuit components such as the transistor resistance, lead inductance, load capacitance, and oscillation frequency of the noise signal. Since the current slew rate is not constant during the device switching, a rigorous analysis to determine the current slew rate was performed. Then a new simple but accurate closed-form SSN model was developed by accurately determining current slew rate for SSN with the alpha-power-law of a sub-micron transistor drain current. The derived SSN model implicitly includes all the critical circuit performance and package parameters. The model is verified with the general-purpose circuit simulator, HSPICE. The model shows an excellent agreement with simulation even in the worst case (i.e., within a 10% margin of error but normally within a 5% margin of error). A package design methodology is presented by using the developed model.

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Fundamental Interconnection Issues

Cited by 24 publications

References 38 publications

A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

Clock distribution networks in synchronous digital integrated circuits

New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design

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