Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

Samavedam, Srikanth; Ryckaert, Julien; Beyne, Eric; Ronse, Kurt G.; Horiguchi, N.; Tőkei, Zsolt; Radu, Iuliana; Bardon, M. Garcia; Na, M. H.; Spessot, A.; Biesemans, S.

doi:10.1109/iedm13553.2020.9372023

Cited by 82 publications

(32 citation statements)

References 39 publications

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“…Therefore, it has become increasingly crucial to optimize device geometry to mitigate SHE as we continue scaling down to extreme dimensions. Furthermore, the structural density and complexity of 3D monolithic integration is expected to aggravate this problem [16]- [20]; yet, the thermal aspects of CFETs have never been thoroughly discussed.…”

Section: Introductionmentioning

confidence: 99%

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic complementary FET (CFET) in DC operation as well as in AC CMOS operation were investigated with TCAD simulations. The self-heating effect (SHE) in a monolithic CFET is expected to be a critical problem given its highly compact architecture. DC analysis of the individual NFET and PFET devices revealed that increasing the channel width from 5.0 to 7.0 nm improved the thermal resistance up to 8.5% and the RC delay up to 9.6%, while greatly deteriorating the on/off ratio. AC CMOS inverter simulations of the CFET showed that reducing the NFET/PFET vertical separation from 30 to 10 nm resulted in 11.9% faster operation frequency and 3.4% reduced dynamic power loss, but 11.2% higher rise in device temperature. The clear trade-off relationships between the thermal and electrical performance factors necessitate optimization of the device dimension parameters. These findings are expected to provide critical insight for the design technology co-optimization (DTCO) in the 3-nm regime.INDEX TERMS Complementary FET (CFET), self-heating effect (SHE), 3D monolithic integration, TCAD, thermal resistance, time delay, figure of merit (FoM), CMOS inverter, device optimization.

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Section: Introductionmentioning

confidence: 99%

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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“…However, to support more scaled process technologies, the half-pitch resolution should be improved. In this context, extreme ultraviolet (EUV) lithography has been proposed assuming that costly new manufacturing equipment will be needed [5]. At the same time, other alternatives to increase the performance of the integrated circuits have been considered.…”

Section: Introductionmentioning

confidence: 99%

“…However, limitations in any of the carrier mobilities (electrons or holes), wider bandgaps and difficulties in their integration into silicon processes have limited the applications in complimentary MOS (CMOS) technology [6]. On the other hand, twodimensional materials, led by the discovery of graphene [9,10], have attracted tremendous attention due to their promising electrical properties [5,11]. Thanks to their low dimensionality, these thin materials present an optimal electrostatic control of the channel [12], flexibility and extremely sensitive capabilities to the changes in their surroundings.…”

Section: Introductionmentioning

confidence: 99%

Hysteresis in As-Synthesized MoS2 Transistors: Origin and Sensing Perspectives

et al. 2021

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Two-dimensional materials, including molybdenum disulfide (MoS2), present promising sensing and detecting capabilities thanks to their extreme sensitivity to changes in the environment. Their reduced thickness also facilitates the electrostatic control of the channel and opens the door to flexible electronic applications. However, these materials still exhibit integration difficulties with complementary-MOS standardized processes and methods. The device reliability is compromised by gate insulator selection and the quality of the metal/semiconductor and semiconductor/insulator interfaces. Despite some improvements regarding mobility, hysteresis and Schottky barriers having been reported thanks to metal engineering, vertically stacked heterostructures with compatible thin-layers (such as hexagonal boron nitride or device encapsulation) variability is still an important constraint to sensor performance. In this work, we fabricated and extensively characterized the reliability of as-synthesized back-gated MoS2 transistors. Under atmospheric and room-temperature conditions, these devices present a wide electrical hysteresis (up to 5 volts) in their transfer characteristics. However, their performance is highly influenced by the temperature, light and pressure conditions. The singular signature in the time response of the devices points to adsorbates and contaminants inducing mobile charges and trapping/detrapping carrier phenomena as the mechanisms responsible for time-dependent current degradation. Far from being only a reliability issue, we demonstrated a method to exploit this device response to perform light, temperature and/or pressure sensors in as-synthesized devices. Two orders of magnitude drain current level differences were demonstrated by comparing device operation under light and dark conditions while a factor up to 105 is observed at vacuum versus atmospheric pressure environments.

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“…To enable more efficient computing, both device and interconnect architectures are expected to change. The device trend from today's conventional FinFet to Nanosheet then Forksheet then to CFET and eventually to 2D materials will be explained [3,5,6]. This is alongside with the wide deployment of EUV lithography into BEOL, MOL, FEOL paving a cost-effective patterning.…”

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confidence: 98%

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confidence: 99%

Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene

Tőkei

2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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An overview of future logic scaling options both for devices and interconnects will be provided from technology point of view, including Front-End-Of-Line (FEOL), Middle-Of-Line (MOL) and Back-End-Of-Line (BEOL) modules [1][2][3][4]. The aim is to provide a perspective for the coming 10years in terms of CMOS scaling scenarios. To enable more efficient computing, both device and interconnect architectures are expected to change. The device trend from today's conventional FinFet to Nanosheet then Forksheet then to CFET and eventually to 2D materials will be explained [3,5,6]. This is alongside with the wide deployment of EUV lithography into BEOL, MOL, FEOL paving a cost-effective patterning. Track height scaling along with the use of scaling boosters is the natural path to follow. It is accompanied by significant changes in MOL and BEOL modules as well. One example is the potential inflection point from classical dual damascene modules towards metal patterning based self-aligned semi damascene. This in combination with airgaps can provide an attractive RC tradeoff. Another example is backside power delivery enabled by the use of nano-TSVs [7,8]. During the talk several more examples will be shown.

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Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

Cited by 82 publications

References 39 publications

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Hysteresis in As-Synthesized MoS2 Transistors: Origin and Sensing Perspectives

Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene

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