G&lt;inf&gt;m&lt;/inf&gt;/I&lt;inf&gt;D&lt;/inf&gt; based noise analysis for CMOS analog circuits

Ou, Jack

doi:10.1109/mwscas.2011.6026580

Cited by 11 publications

(12 citation statements)

References 3 publications

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“…This observation is true for any two parameters whose ratio depend solely on the g m /I D and not on the width of a transistor. The list of parameters that do not depend on the width of a transistor include current density, transit frequency, device noise corner frequency and thermal noise coefficient [2]. Once a transistor of a given width (W ) is characterized over a range of g m /I D , the g m /I D based parameters can be generalized to a transistor of an arbitrary width.…”

Section: A Fundamentalsmentioning

confidence: 99%

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Transconductance/drain current based sensitivity analysis for analog CMOS integrated circuits

Ou¹,

Farahmand²

2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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Recent studies have shown that transistor variability and ageing phenomena are responsible for variation of transconductance (gm) and drain current (ID) in MOSFETs. It is therefore important to perform sensitivity analysis at the earliest design stage in order to minimize effects of ageing. It is however not trivial to perform sensitivity analysis analytically because the I-V characteristics of modern transistors can not modeled without using complicated expressions. In this paper, We propose a technique that utilizes the transconductance-to-drain current ratio (gm/ID) of a transistor to captures the sensitivity of a circuit. This technique is applicable to transistors biased in all regions of operations. To explore the effectiveness of the proposed technique in practical circuit design, the sensitivity of a common source amplifier is analyzed. The proposed technique has an accuracy of ± 15 % between 4 < gm/ID < 28.

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Section: A Fundamentalsmentioning

confidence: 99%

“…Building on Jespers' work, we have reported a g m /I D based noise analysis that utilized bias dependent thermal noise coefficient and device noise corner frequency to characterize device noise [2] and a technique to characterize transistor nonlinearity [3].…”

Section: Introductionmentioning

confidence: 99%

Transconductance/drain current based sensitivity analysis for analog CMOS integrated circuits

Ou¹,

Farahmand²

2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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“…Silveira's original work led to the development of two different formulations of g m /I D -dependent noise parameters in the literature. The first formulation was published by Ou [4] in 2011. Bias-dependent thermal noise coefficient (γ) and device noise corner frequency (f co ) were introduced and extracted from transistor-level simulations.…”

Section: Introductionmentioning

confidence: 99%

A <inline-formula> <tex-math notation="TeX">$g_{m}/I_{D}$</tex-math></inline-formula>-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier

Ferreira

2014

IEEE Trans. Circuits Syst. II

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Noise optimization is a challenging problem for nanoscale metal-oxide-silicon field-effect transistor circuits. This brief presents a technique that uses transconductance-to-drain current (g m /I D )-dependent transistor-noise parameters to explore the design space and to evaluate tradeoff decisions. An expression for the corner frequency of the folded-cascode amplifier is derived. The design process demonstrated in this brief using the folded-cascode amplifier is applicable to a wide class of amplifier circuits.Index Terms-Analog circuit design, g m /I D circuit design, noise analysis.

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“…The g m /I D design methodology was originally proposed in [2]-[3] and extended to incorporate noise analysis in [4]. A survey of the published literature indicates that there is no prior publication on g m /I D based distortion analysis.…”

Section: Introductionmentioning

confidence: 99%

“…INTRODUCTION g m /I D design methodology is a powerful technique that allows designers to quickly size up transistors. The g m /I D design methodology was originally proposed in [2]- [3] and extended to incorporate noise analysis in [4]. A survey of the published literature indicates that there is no prior publication on g m /I D based distortion analysis.…”

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confidence: 99%

Transconductance/drain current based distortion analysis for analog CMOS integrated circuits

Ou¹,

Farahmand²

2012

10th IEEE International NEWCAS Conference

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This paper proposes a technique to analyze distortion in analog CMOS integrated circuits. The proposed technique captures a transistor's nonlinearity using a twodimensional Taylor series with coefficients that depend on the transconductance-to-current ratio (gm/ID) of a transistor. To explore the effectiveness of the proposed technique, a commonsource amplifier is designed. The harmonics of the amplifier are calculated using both the gm/ID technique and Cadence's periodic steady state (PSS) analysis over a wide range of gm/ID. The results indicate a close match (i.e. a discrepancy less than 2 dB from gm/ID=8 to 30) and show that the proposed technique can indeed be incorporated in a gm/ID design flow. I. INTRODUCTIONg m /I D design methodology is a powerful technique that allows designers to quickly size up transistors. The g m /I D design methodology was originally proposed in [2]-[3] and extended to incorporate noise analysis in [4]. A survey of the published literature indicates that there is no prior publication on g m /I D based distortion analysis. This paper describes a procedure to include distortion as part of the g m /I D design flow. Section II describes the underlying principles of g m /I D design flow, introduces a two-dimensional Taylor series approximation, and describes means of obtaining g m /I D based Taylor series coefficients. Section III analyzes the distortion of a common-source amplifier as a means to compare g m /I D based design to Cadence simulation. Section IV describes the limitations of g m /I D based distortion analysis.

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G<inf>m</inf>/I<inf>D</inf> based noise analysis for CMOS analog circuits

Cited by 11 publications

References 3 publications

Transconductance/drain current based sensitivity analysis for analog CMOS integrated circuits

Transconductance/drain current based sensitivity analysis for analog CMOS integrated circuits

A <inline-formula> <tex-math notation="TeX">$g_{m}/I_{D}$</tex-math></inline-formula>-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier

Transconductance/drain current based distortion analysis for analog CMOS integrated circuits

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