GaAsSb/InGaAs double-gate vertical tunnel FET with a subthreshold slope of 56 mV dec⁻¹ at room temperature

Abstract

We fabricated double-gate vertical GaAsSb/InGaAs tunnel FETs (TFETs). The characteristics of these TFETs were improved by changing the gate electrode evaporation from the electron beam to thermal evaporation. Furthermore, by changing the insulator from Al2O3/HfO2 to Al2O3/ZrO2, the steepest subthreshold slope (SS) = 56 mV dec−1 at VDS = 0.2 V was achieved. We analyzed these devices in two ways. First, to investigate the influence of trap-assisted tunneling (TAT), we conducted low-temperature measurements and found that TAT was suppressed through thermal evaporation. Next, to estimate the limitation of the SS, the energy decay parameter E0 was estimated from the negative differential resistance characteristics. Energy decay parameter E0 is determined by the impurity level and becomes a leak component of the TFET. However, we found that energy decay parameter E0 is both process and temperature-dependent.

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

“…We fabricated this device by stacking GaAsSb/InGaAs on an InP substrate. 14,16,21) In this case, the component ratio that can be used for GaAsSb/InGaAs is limited in order to achieve lattice matching with InP. However, by using the recently proposed metamorphic buffer layer 31) or nanosheet structure, 32,33) various component ratios can be used if lattice matching between GaAsSb and InGaAs is achieved without concern for the lattice of the underlying substrate.…”

“…Steep switching devices are currently being researched in an effort to prolong the scaling merit of LSI and achieve lower power consumption. [6][7][8][9][10][11] Among these steep switching devices, the tunnel FET is a promising alternative to CMOS and has been studied extensively both experimentally [12][13][14][15][16][17][18][19][20][21] and theoretically. [22][23][24][25][26][27][28] Despite aiming for steep switching, most studies on TFETs face the challenge of TFETs not being steep due to the lack of on-current or high off-current.…”

“…Recently, GaAsSb/InGaAs double-gate hetero-junction tunnel FETs have achieved steep switching at 60 mV/decade at room temperature. 21) This is the result of utilizing an improved gate insulator; moreover, theoretical studies demonstrate that better performance can be achieved by reducing body thickness. 16) Thus, the III-V double-gate hetero-junction tunnel FET is encouraging, but its device design principle is unclear.…”

GaAsSb/InGaAs tunnel FETs using thick SiO2 mask for regrowth

“…One promising material combination for TFETs is In(Ga)As/Ga(As)Sb. [3][4][5][6][7][8][9] In(Ga)As/Ga(As)Sb heterojunctions provide staggered or broken energy-band alignments, enabling a high current density for TFETs. The technology used for Si CMOS gates is not applicable to vertical heterojunction devices with continuous crystal growth.…”

“…The technology used for Si CMOS gates is not applicable to vertical heterojunction devices with continuous crystal growth. [4][5][6][7][8] Assessing the interface state density or mobility on vertical sidewalls is challenging due to the limited channel height, although these measurements are vital for device analysis. The lateral growth of heterojunctions 3,9) offers a solution to these challenges; however, it necessitates selective growth, i.e.…”