GaN and Si Transistors on 300mm Si(111) Enabled by 3D Monolithic Heterogeneous Integration

Then, Han Wui; Radosavljević, M.; Agababov, P.; Ban, I.; Bristol, Robert; Chandhok, Manish; Chouksey, S.; Holybee, B.; Huang, Chao‐Wei; Krist, B.; Jun, Kimin; Koirala, Pratik; Lin, Kevin L.; Michaelos, T.; Paul, R.; Peck, J.; Rachmady, W.; Staines, D.; Talukdar, Tushar K.; Thomas, N.; Tronic, Tristan A.; Fischer, P.; Hafez, W.

doi:10.1109/vlsitechnology18217.2020.9265093

Cited by 17 publications

(6 citation statements)

References 2 publications

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“…We also compare our upper‐layer FETs with the upper‐layer FETs in other reported M3D technologies containing at least two‐layer transistors (Figure 3F). The I on of our upper‐layer FETs outperforms that of most Si/Ge‐based FETs whose performance is constrained by poor upper channel materials and thermal budget‐limited fabrication processes 41,42,53–63 . Compared to other emerging materials, such as oxide semiconductor‐, III ‐ V group‐, organic semiconductor‐ and transition metal dichalcogenide (TMD)‐based upper‐layer FETs, 30–34,40,64–68 our upper‐layer A‐CNT FETs present a much higher current driving capacity, mainly owing to the high carrier mobility of transferred A‐CNTs and smooth ILD surface.…”

Section: Performance Of Bottom‐ and Upper‐layer A‐cnt Fetsmentioning

confidence: 94%

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Fan

Cheng

et al. 2023

InfoMat

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Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date.

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Section: Performance Of Bottom‐ and Upper‐layer A‐cnt Fetsmentioning

confidence: 94%

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Fan

Cheng

et al. 2023

InfoMat

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“…Keisuke Shinohara et al [142] demonstrated the most suitable T-gate shape through simulation based on gate capacitance as show in Figures 10 and 11. Benchmark of cut-off frequency versus L G [143][144][145][146][147][148] illustrates the importance of gate length shrinking to increase f T . Both NTU [149] and Intel [143] demonstrated 40 nm gate length GaN HEMT on Si with f T /fmax higher than 300 GHz, though the current record f T /fmax values of 450 GHz was achieved by HRL [144] with the 20 nm Gate GaN on SiC technology.…”

Section: Rf Gan Performance Si Substratementioning

confidence: 99%

“…Benchmark of cut-off frequency versus L G [143][144][145][146][147][148] illustrates the importance of gate length shrinking to increase f T . Both NTU [149] and Intel [143] demonstrated 40 nm gate length GaN HEMT on Si with f T /fmax higher than 300 GHz, though the current record f T /fmax values of 450 GHz was achieved by HRL [144] with the 20 nm Gate GaN on SiC technology. GaN HEMT on Si also have high load pull result comparable to SiC substrate [155], nevertheless, GaN HEMT on Si substrate shows high potential.…”

Section: Rf Gan Performance Si Substratementioning

confidence: 99%

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

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GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

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“…Among the heterojunction device structures, the AlGaN/GaN HEMT exhibits the best electronic characteristics [9][10][11]. Furthermore, the AlGaN/GaN-on-Si is the structure most commonly selected for power application for the following reasons [12][13][14][15]: the fabrication process is compatible with Si CMOS process flow, which helps to reduce the manufacturing cost. Realization of a large-size AlGaN/ GaN-on-Si wafer can also further reduce the cost.…”

Section: Introductionmentioning

confidence: 99%

Process of Au-Free Source/Drain Ohmic Contact to AlGaN/GaN HEMT

Zhang

Miao

et al. 2022

Crystals

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AlGaN/GaN high electron mobility transistors (HEMTs) are regarded as promising candidates for a 5G communication system, which demands higher frequency and power. Source/drain ohmic contact is one of the key fabrication processes crucial to the device performance. Firstly, Au-contained metal stacks combined with RTA high-temperature ohmic contact schemes were presented and analyzed, including process conditions and contact formation mechanisms. Considering the issues with the Au-contained technique, the overview of a sequence of Au-free schemes is given and comprehensively discussed. In addition, in order to solve various problems caused by high-temperature conditions, novel annealing techniques including microwave annealing (MWA) and laser annealing (LA) were proposed to form Au-free low-temperature ohmic contact to AlGaN/GaN HEMT. The effects of the annealing method on surface morphology, gate leakage, dynamic on-resistance (RON), and other device characteristics are investigated and presented in this paper. By using a low-temperature annealing atmosphere or selective annealing method, gate-first Si-CMOS compatible AlGaN/GaN HEMT technology can be realized for high frequency and power application.

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GaN and Si Transistors on 300mm Si(111) Enabled by 3D Monolithic Heterogeneous Integration

Cited by 17 publications

References 2 publications

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Process of Au-Free Source/Drain Ohmic Contact to AlGaN/GaN HEMT

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