Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels

Tsai, Jung-Ruey; Lee, Ko Hui; Lin, Horng−Chih; Huang, Tiao‐Yuan

doi:10.7567/jjap.53.04ed14

Cited by 5 publications

(1 citation statement)

References 13 publications

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“…[1][2][3] Various concepts for flash memories have been proposed to achieve high density. [4][5][6][7][8][9] However, the scaling limitation and manufacturing difficulties will be confronted in the near future for conventional NAND technology. In order to overcome these problems, several three-dimensional (3D) technologies, such as Bit-Cost Scalable (BiCS), [10][11][12][13][14][15][16][17][18] SMArT 19,20) and terabit cell array transistor (TCAT) flash technologies, 13,21,22) have been introduced.…”

Section: Introductionmentioning

confidence: 99%

Device characteristics of the select transistor in a vertical-NAND flash memory

Kang

Park

Kim

et al. 2023

Jpn. J. Appl. Phys.

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In this paper, variation in parameters of select transistor of V(Vertical)-NAND flash memory is investigated for device optimization and performance evaluation. Device characteristics including threshold voltage (VTH), subthreshold swing (SS) and Off-current (IOFF) are evaluated with device parameters and those evaluations are performed with two dimensional device simulation. An equivalent structure of VNAND flash memory select transistor is suggested which includes a fully depleted silicon on insulator (SOI) MOSFET region and a bulk MOSFET region. Effects of device parameter on device performances of select transistor are investigated with physical modeling with focusing on two merged MOSFET structures. Vertical channel thickness and channel scaling affect on VTH, SS and IOFF respectively. However, corner shape in select transistor has a negligible effects on device performance. Design guidance of select transistor in V-NAND flash memory can be provided by simulation results in this work.

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Section: Introductionmentioning

confidence: 99%

Device characteristics of the select transistor in a vertical-NAND flash memory

Kang

Park

Kim

et al. 2023

Jpn. J. Appl. Phys.

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Ultra-high aspect ratio poly-Si FinFET using an improved spacer formation technique

Liu

Liang

Wang

et al. 2017

Superlattices and Microstructures

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Floating gate potential of gate-all-around floating gate memory cell: parameter extraction and compact model

Hamzah,

Alias,

Johari

et al. 2024

Phys. Scr.

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The compact modeling of NAND flash memories is crucial for integrated circuit designers to carry out efficient and precise circuit-level evaluations, particularly in the case of 3D NAND flash where the 3D geometry leads to significant parasitic coupling impacts on performance. In this work, we proposed a charge-based modeling approach for gate-all-around floating gate memory cells. The compact model is based on the derived unified charge control model where the mobile charge is explicitly solved. By solving the charge balance model and taking into account voltage-dependent parasitic capacitances for accurate coupling effects, the floating gate potential is accurately computed. The simulation results are validated with numerical TCAD simulation and showed good agreement with TCAD simulation. By solving the charge balance model and considering voltage-dependent parasitic capacitances for more accurate coupling effects, the floating gate potential is accurately calculated. The simulation results were validated using numerical TCAD simulation and showed good agreement, demonstrating that the floating gate potential is accurately estimated through the inclusion of voltage-dependent parasitic capacitances. Additionally, the results indicate that subthreshold degradation is caused by interface trap charge in the experimental device, and the proposed model successfully replicates experimental data.

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Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels

Cited by 5 publications

References 13 publications

Device characteristics of the select transistor in a vertical-NAND flash memory

Device characteristics of the select transistor in a vertical-NAND flash memory

Ultra-high aspect ratio poly-Si FinFET using an improved spacer formation technique

Floating gate potential of gate-all-around floating gate memory cell: parameter extraction and compact model

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