Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

Fung, S.K.H.; Khare, Mukesh; Schepis, D.; Lee, Woo-Hyeong; Ku, S.H.; Park, H.; Snare, J.; Doris, B.; Ajmera, A.; Müller, K.P.; Agnello, P.; Gilbert, P.; Welser, J.J.

doi:10.1109/iedm.2001.979587

Cited by 7 publications

(5 citation statements)

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“…The use of SOI has made it possible to reduce the perimeter junction capacitance (as compared to bulk CMOS) by using thinner SOI (Figure 9) [12]. Indeed, using thin SOI films allows one to use higher doping concentrations in the halos, thus reducing SCE [7]. Going to thinner films has a noticeable impact on device performance.…”

Section: Figurementioning

confidence: 99%

“…As we move forward, SOI CMOS technology development is completed for the 0.13-m generation [6,20] and has been initiated for the 0.1-m generation [7,27]. These technologies are simply the highest-performance CMOS in production.…”

Section: Futurementioning

confidence: 99%

“…A limited number (a few tens of thousands) of 32-bit PowerPC 750* microprocessors, using 0.22-m CMOS SOI, were also shipped to customers. Since then, the development has focused on 0.18-m [5], 0.13-m [6], and 0.1-m [7] CMOS SOI technologies, with a greatly increased customer base.…”

Section: Introductionmentioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

174

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Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-m generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-m generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

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Section: Figurementioning

confidence: 99%

Section: Futurementioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

174

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“…Since there is a tradeoff between the short-channel effects Manuscript and in the halo process, the simultaneous optimization of short-channel effects and is a challenge in advanced CMOS technologies. One of the proposed solutions is to migrate to silicon-on-insulator (SOI) substrates, which helps reduce even with high halo doses [3]. However, SOI is not cost-effective for some applications and also results in floating body effects.…”

Section: Introductionmentioning

confidence: 99%

“…As a consequence, the short-channel effects are dramatically improved by halo process without the need for extreme scaling of S/D junction depth. However, the halo process has a serious shortcoming -increase in the parasitic junction capacitance ( ) [3]. It is well known that increases with halo implant dose [4].…”

Section: Introductionmentioning

confidence: 99%

Simultaneous optimization of short-channel effects and junction capacitance in pMOSFET using large-angle-tilt-implantation of nitrogen (LATIN)

Lee

Murthy

Rengarajan

et al. 2002

IEEE Electron Device Lett.

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A widely used halo implant process of counter doping has a tradeoff between the short channel effects and the parasitic junction capacitance. In this letter, we propose a novel drain engineering concept, large-angle-tilt-implantation of nitrogen (LATIN) to improve the short-channel effects without the increase of the junction capacitance in the buried-channel pMOSFET using sub-0.25-m CMOS technology. We compare the electrical characteristics of devices fabricated using LATIN, a conventional arsenic halo implant process (As HALO), and BF + 2 source/drain (S/D) implantation only. The LATIN improves the short-channeleffects when compared to the case of BF + 2 S/D implant only. In addition, the LATIN reduces junction capacitance by 18% when compared to As HALO. As a consequence, the LATIN is shown to be a drain engineering concept to simultaneously optimize the short-channel effects and junction capacitance. Calibrated two-dimensional simulations confirm the improvement with LATIN.

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Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

Chan

Wan

et al. 2004

Solid-State Electronics

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Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology

Cited by 7 publications

References 0 publications

SOI technology for the GHz era

SOI technology for the GHz era

Simultaneous optimization of short-channel effects and junction capacitance in pMOSFET using large-angle-tilt-implantation of nitrogen (LATIN)

Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

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