General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

“…This is important, because the shape of the jitter spectrum has a significant influence on the total amount of in-band jitter-caused noise at the output of the modulator, even if the total clock jitter power remains unchanged. This was already shown in several more recent papers, which did include the effect of the jitter spectrum ( [5,6]) on the CTSDM's performance.…”

“…For a CTSDM with high loop gain and a NRZ DAC pulse, neglecting the second order jitter term was shown to be very accurate by the theory in [5], and simulation results seem to indicate that it remains accurate for SOSDMs. To calculate y 0 , the output signal of the modulator in the absence of jitter, we will use Eq.…”

“…It is well known that a jittered clock degrades the performance of a continuous time sigma delta modulator ( [2,5,6]). In the following, we will apply the analysis of [2] on SOSDMs.…”

Delay‐compensation block for first‐order low‐pass delta‐sigma modulators

“…Previous works focused on the sub‐period characterization of the sources of the delay by investigating the excess loop delay and proposed different methods to compensate for it . Other works have investigated the effect of group‐delay, jitter and the frequency response . For this paper, we focus on the discrete‐time delay impact which appears when implementing the DSM on an field programmable gate array (FPGA) using blocks running at the same clock rate.…”

“…2 Other works have investigated the effect of group-delay, 3 jitter and the frequency response. 4 For this paper, we focus on the discretetime delay impact which appears when implementing the DSM on an field programmable gate array (FPGA) using blocks running at the same clock rate. To investigate the effect of the delays, we modeled the sources of discrete delays using a generic model using the first order DSM transfer function.…”