Generating high-performance custom floating-point pipelines

Abstract

Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators are costly to design, and application designers tend to rely on less efficient off-the-shelf operators. To address this issue, an open-source architecture generator framework is introduced. Its salient features are an easy learning curve from VHDL, the ability to embed arbitrary synthesizable VHDL code, portability to mainstream FPGA targets from Xilinx and Altera, automatic management of complex pipelines with support for frequency-directed pipeline, and automatic test-bench generation. This generator is presented around the simple example of a collision detector, which it significantly improves in accuracy, DSP count, logic usage, frequency and latency with respect to an implementation using standard floating-point operators.

SMI: Slack Measurement Insertion for online timing monitoring in FPGAs

“…We applied the SMI tool flow to three benchmark circuits: a single precision floating point adder, multiplier and divider, generated by FloPoCo [5]. The resource usage of the benchmarks and the model-predicted maximum operating frequency (F max ) are given in Table 1.…”

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

“…RELATED WORK Tenca [6] introduced a 3-input floating-point adder that achieves reduced error compared to two IEEE floating-point adders; however, this approach requires the precision of the effective operation to increase from f to 2f+5; this approach is unlikely to scale for more than three or four operands. The FloPoCo compiler [7] can also generate effective 3-input operations when necessary, and can eliminate effective subtraction when all input operands are known to be positive, e.g., when computing x 2 + y 2 + z 2 . Our approach, in contrast, takes the same approach as Altera's floating-point datapath compiler [1,2], and scales up to 16 operands, while improving upon both area and delay.…”

A parameterized floating-point exponential function for FPGAs

“…This work was also an in-depth case study for the pipeline generator framework of FloPoCo [15]. This framework enables easy composition and synchronization of components that pipeline themselves to run at a user-provided frequency.…”

“…It comes with test vector generation [15]. In general, it should be immediately usable for application designers.…”

“…In addition, many targetspecific optimizations are performed by the FloPoCo framework [15], [16], [17].…”