Generic Electrostatic Discharges Protection Solutions for RF and Millimeter-Wave Applications

Lim, Thomas; Benech, Philippe; Jiménez, José Luis Ubera; Fournier, Jean‐Michel; Heitz, B.; Bourgeat, Johan; Galy, Philippe

doi:10.1109/tmtt.2015.2478000

Cited by 8 publications

(1 citation statement)

References 24 publications

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“…The circuitry consists of a pair of high-side and low-side diodes that direct the ESD current from input/ output (IO) pins to power supply (VDD) and ground rail (GND). The ESD discharging path between VDD and GND, formed by the primary ESD cell, is shared by two or more IO pins [22,23,24]. When multiple IO pins share one primary ESD cell, total chip area consumed by ESD circuits is reduced.…”

Section: Introductionmentioning

confidence: 99%

Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Lai

Wang

et al. 2019

IEICE Electron. Express

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In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based ESD protection circuits was investigated. The device simulation results show that the triggering voltage of the parasitic PNP varies with the geometry of the base region (e.g., the spacing between P+ and N-well). Furthermore, the test structures of parasitic PNP devices with different width of collector and base region were fabricated using the 65 nm low-k logic/Mixed-Mode CMOS process and characterized with the transmission line pulse (TLP) system. Both simulation and experimental results demonstrated that the triggering voltage of parasitic PNP structures has strong dependence on the base region and the simulation results also show that the triggering voltage is significantly affected by the spacing between P-well and N-well.

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Section: Introductionmentioning

confidence: 99%