GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

Hutin, Louis; Royer, C. Le; Damlencourt, J.-F.; Hartmann, J.-M.; Grampeix, H.; Mazzocchi, V.; Tabone, C.; Prévitali, B.; Pouydebasque, A.; Vinet, M.; Faynot, O.

doi:10.1109/led.2009.2038289

Cited by 121 publications

(59 citation statements)

References 13 publications

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“…The fact that V th decreases while S increases with increasing EOT as observed from the figure can be explained by accounting for the weaker value of gate field for a larger EOT. Experimentally such degradation of sub-threshold swing for GeOI pMOSFETs is observed as the channel length is reduced [16]. Further extensive simulation studies of Krishnamohan et al [38] on strained Ge channel DG MOSFETs show similar degradation of sub-threshold slope as the channel length is reduced.…”

Section: Resultsmentioning

confidence: 79%

“…There have been several experimental reports in the literature [12][13][14][15][16] involving growth, characterization and studies of electrical behavior of Ge-channel p-MOSFETs with high-k dielectrics. Many attempts have been made with various high-k materials, including HfO 2 , ZrO 2 , Al 2 O 3 and LaAlO 3 to find a suitable insulator for Ge [13,17].…”

Section: Introductionmentioning

confidence: 99%

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Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

Bhattacherjee¹,

Biswas²

2011

Microelectronics Reliability

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Section: Resultsmentioning

confidence: 79%

Section: Introductionmentioning

confidence: 99%

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

Bhattacherjee¹,

Biswas²

2011

Microelectronics Reliability

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“…An atomic monolayer of Si was selflimitedly grown in 5 min at 450 1C then thickened at 525 1C (1.8Å min À 1 ) thanks to SiH 4 at 20 Torr. Such a LT Ge surface passivation with SiH 4 yields state-of-the art p-MOSFETs [6,40,41] provided that a 15Å Si layer thickness is not exceeded. Elastic relaxation of the tensile strain (through the formation of numerous 2D islands 5-15Å high and a few tens of nm in diameter) indeed occurs for higher Si thicknesses.…”

Section: Resultsmentioning

confidence: 99%

Impact of the H2 anneal on the structural and optical properties of thin and thick Ge layers on Si; Low temperature surface passivation of Ge by Si

Hartmann

Abbadie

Barnes

et al. 2010

Journal of Crystal Growth

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“…The calculated effective hole mobility is plotted as a function of the carrier density (N s ) in Figure 5b. The effective hole mobility at V gs = 0 was larger than 230 cm 2 2:1:4000 mixture) at 5…”

mentioning

confidence: 95%

“…1 The combination of the advantages of Ge and on-insulator substrates, such as the reduced junction capacitances and better electrostatic control, has led germanium-on-insulator (GOI) substrates to be considered to have extensive application prospects. 2,3 Many methods have been investigated to fabricate GOI, such as Ge condensation techniques, 4 liquid phase epitaxy, 5 and layer transfer techniques. 6 Ultrathin body (UTB) GOI is a promising substrate for advanced complementary metal-oxide-semiconductor devices, such as junctionless transistors (JLTs).…”

mentioning

confidence: 99%

Preparation of Ultrathin Germanium on Insulator Films Using a Wet Etching Process

Sun

Liang

Wang

et al. 2015

ECS Solid State Letters

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We demonstrate a wet etching method to reduce the thickness of thin germanium-on-insulator (GOI) films using a dilute solution (a NH 4 OH:H 2 O 2 :H 2 O 2:1:4000 mixture) at a low temperature (5 • C). The etch rate and thickness uniformity were well controlled. The root mean square roughness after wet etching was less than 0.5 nm and did not degrade compared with the original sample. Finally, back gate junctionless transistors were fabricated using the GOI wafers with 15-nm-thick Ge films, thinned by the developed method. The transistors had good I on /I off ratio and mobility qualities, indicating that the wet etching process effectively thinned the Ge films. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0021506ssl] All rights reserved.Manuscript submitted December 30, 2014; revised manuscript received March 16, 2015. Published March 31, 2015 As the feature size of transistors is further reduced to the nanometer scale, Ge is regarded as a promising candidate for use in future transistors because of its high electron and hole mobility compared with Si.1 The combination of the advantages of Ge and on-insulator substrates, such as the reduced junction capacitances and better electrostatic control, has led germanium-on-insulator (GOI) substrates to be considered to have extensive application prospects.2,3 Many methods have been investigated to fabricate GOI, such as Ge condensation techniques, 4 liquid phase epitaxy, 5 and layer transfer techniques. 6 Ultrathin body (UTB) GOI is a promising substrate for advanced complementary metal-oxide-semiconductor devices, such as junctionless transistors (JLTs). 3,7,8 However, fabricating high-quality UTB GOI substrates directly using the existing methods is difficult, so it is necessary to develop a thinning method to prepare UTB GOI substrates, similar to those used with UTB SOI substrates. 9,10Wet etching is widely used in the semiconductor industry for wafer cleaning and defect revelation. 11 In the literature, studies on wet etching bulk Ge are limited, let alone GOI. Ge is not very reactive with single acid and alkali solutions, but it is easily oxidized and its oxide (GeO 2 ) is soluble in aqueous solutions. Therefore, wet etching Ge is usually conducted in a solution containing an oxidizing agent. Brunco et al. 15,16 listed the etch rates of bulk Ge in several different chemicals. However, to prepare UTB GOI substrate, the thickness to remove is often very small, so etch rate need to be well controlled. In addition, owing to the special preparation processes, the etch rate of GOI may not be constant with time and may differ from that of bulk Ge. To obtain ultrathin (less than 15 nm) Ge films, the reported etching methods need to be optimized. Though the feasibility of preparing UTB GOI using we...

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GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

Cited by 121 publications

References 13 publications

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

Impact of the H2 anneal on the structural and optical properties of thin and thick Ge layers on Si; Low temperature surface passivation of Ge by Si

Preparation of Ultrathin Germanium on Insulator Films Using a Wet Etching Process

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