Globally asynchronous locally synchronous architecture for large high-performance ASICs

Meincke, T.; Hemani, Ahmed; Kumar, S.; Ellervee, Peeter; Öberg, Johnny; Olsson, Thomas; Nilsson, Peter; Lindqvist, Dan; Tenhunen, Hannu

doi:10.1109/iscas.1999.780794

Cited by 28 publications

(12 citation statements)

References 7 publications

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“…Another common approach to reduce the power and energy consumption in CMPs and SoCs is the use of a globally-asynchronous, locally synchronous (GALS) clocking scheme [3]. In traditional VLSI design, a single synchronized clock is maintained throughout the entire chip.…”

Section: Introductionmentioning

confidence: 99%

“…These synchronized architectures require fully balanced clock distribution trees to ensure minimal clock skew between communicating components. Fully balanced clock distribution trees, however, consume a significant portion of the total chip power which can be as high as 30% of the total power consumed by the chip [3]. On-chip power consumption can be reduced by replacing the balanced clock tree with a GALS clocking scheme which only guarantees minimal clock skew within the local processing element.…”

Section: Introductionmentioning

confidence: 99%

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Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Jain

Gratz

Sprintson

et al. 2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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Abstract-Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at intermediate nodes between source and destination. In this paper, we propose a novel router microarchitecture which offers superior performance versus typical synchronizing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 50%.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Jain

Gratz

Sprintson

et al. 2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

View full text Add to dashboard Cite

show abstract

“…Nevertheless, the systems are becoming larger (MCM and SoC) and frequencies faster, then the problem of TOF is worst and nets that optimally distribute the clock signal are required [1]. New techniques have been proposed to solve this problem in clock distribution networks (CDNs); some techniques offer solutions at the process or fabrication levels such as the flipchip package [1]; or at the architecture level as asynchronous communication between blocks [7]; or the use of interconnected rings or oscillators as the (local net) CDNs [8]- [12]. The interconnected rings technique has proved to generate, lock and feed a clock signal to more than one chip in a reliable way [9] and has been used for quadrature generators and with a sleep mode [10].…”

Section: Introductionmentioning

confidence: 99%

Analysis and verification of interconnected rings as clock distribution networks

Maza

Aranda

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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The use of interconnected rings approach, as globally asynchronous, locally synchronous clock distribution network, offers good performance regarding scalability, low clock-skew and high-speed clocking. Moreover, they show linear metal-cost growth and the power consumption is directly proportional to number of interconnected rings. In this paper, the performance of interconnected rings, working as clock distribution networks, is analyzed and verified by experimental measurements. Typical 3.3V 0.35µm CMOS N-well AMS process parameters were used for the analysis and chip fabrication. It is shown that interconnected rings are a robust approach under parameters variations.

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“…New techniques have been proposed to solve this problem in clock distribution networks (CDNs); some techniques offer solutions at the process or fabrication levels such as the flip-chip package [1]; or at the architecture level as asynchronous communication between blocks [2]; or the use of interconnected rings as the CDNs [3]. This last approach showed several advantages such as good performance regarding scalability, low clock skew, and high-speed clocking.…”

Section: Introductionmentioning

confidence: 99%

Interconnected rings and oscillators as gigahertz clock distribution nets

Maza¹,

Aranda²

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03

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The performance of interconnected rings and oscillators, working as clock distribution networks, is analyzed and compared among several configurations. The use of interconnected 3-inverter rings as globally asynchronous, locally synchronous clock distribution networks is proposed even for chip lengths from 4 to 24 mm. In this approach, modularity and basic cell properties are kept while the power consumption results directly proportional to the number of blocks. Typical 3.3V AMS 0.35µm CMOS N-well process parameters were used for the analysis. Regarding the current area expansion, we show that interconnected rings is a more robust approach than the interconnected oscillators.

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Globally asynchronous locally synchronous architecture for large high-performance ASICs

Cited by 28 publications

References 7 publications

Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Analysis and verification of interconnected rings as clock distribution networks

Interconnected rings and oscillators as gigahertz clock distribution nets

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