Going beyond worst-case specs with TEAtime

Uht, Augustus K.

doi:10.1109/mc.2004.1274004

Cited by 46 publications

(28 citation statements)

References 7 publications

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“…This is connected to the Monitor and Voltage Control unit as an input. There are different type of errors [11] presented from time to time but this is hardware generated comparative error.…”

Section: Mac Unit Nreset Clockmentioning

confidence: 99%

An in-Situ Timing-Error Prediction and Prevention Technique for Variation-Tolerant Mac-Unit.

Singh¹,

Saha²,

Pahuja³

2017

IJAR

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…………………………………………………………………………………………………….... Introduction:-In deep submicron Integrated Circuits (IC) technologies, process-induced parameter variations cause performance fluctuations, which is an important challenge to be addressed. Due to this, the traditional worst-case methodology of design is no more effective as process variations require more design margins. To deal with this problem, the prediction of parameter variations can play a vital role in manufacturability of silicon devices [1,2,3]. Lower technology nodes are setting a trend of lowering supply-voltage and tremendous increase in clock frequency. These changes of voltage and temperature variations make the design more and more tedious. To achieve a robust design along with above discussed constraints, designers are focusing on Design for Manufacturability (DFM), which is a key to solve these serious problems. As the worst cases rarely occur, so it is always better for the designers to focus on typical cases, called as typical-case design methodology. In recent time, different typical-case design methodologies are proposed, such as Razor circuit [4][5]

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Section: Mac Unit Nreset Clockmentioning

confidence: 99%

An in-Situ Timing-Error Prediction and Prevention Technique for Variation-Tolerant Mac-Unit.

Singh¹,

Saha²,

Pahuja³

2017

IJAR

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“…The first is an infinite impulse response (IIR) filter and, the second, a TEAtime [8], [9] implementation.…”

Section: B Control Block Implementationsmentioning

confidence: 99%

“…Another difference with common IIR filters is the k * gain (Fig. 5) added to ensure the fulfilment of constraints in (8) when the IIR has more than one coefficient. Also we added an extra delay after k * gain in order to take into account the possible necessity to pipeline the control block initial adder.…”

Section: B Control Block Implementationsmentioning

confidence: 99%

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

Pérez-Puigdemont

Calomarde

Moll

2012

2012 IEEE International SOC Conference

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Abstract-In this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This increase in uncertainty forces to add more safety margins to the clock period which produces a circuit performance downgrade. We evaluate three self-adaptive clock systems: free running ring oscillator, infinite impulse response filter controlled RO and TEAtime controlled ring oscillator. The safety margin reduction of the three alternatives is investigated under different clock distribution delay conditions, dynamic variation frequencies and the presence of mismatch between the ring oscillator and the critical paths and the delay sensors.

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“…Recently, these techniques have been used for online timing and soft error recovery in systems. The TEAtime [12] architecture tracks logic delay variations and dynamically adjusts the clock frequency to accommodate the changes in logic delay. In Razor [10], [11], an aggressive better-than-worst-case design approach is presented for processor pipelines.…”

Section: Previous Workmentioning

confidence: 99%

Timing-Error-Tolerant Network-on-Chip Design Methodology

Tamhankar

Murali

Stergiou

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With technology scaling, the wire delay as a fraction of the total delay is increasing, and the communication architecture is becoming a major bottleneck for system performance in systems on chip (SoCs). A communication-centric design paradigm, networks on chip (NoCs), has been proposed recently to address the communication issues of SoCs. As the geometries of devices approach the physical limits of operation, NoCs will be susceptible to various noise sources such as crosstalk, coupling noise, process variations, etc. Designing systems under such uncertain conditions become a challenge, as it is harder to predict the timing behavior of the system. The use of conservative design methodologies that consider all possible delay variations due to the noise sources, targeting safe system operation under all conditions will result in poor system performance. An aggressive design approach that provides resilience against such timing errors is required for maximizing system performance. In this paper, we present T-error, which is a timing-error-tolerant aggressive design method to design the individual components of the NoC (such as switches, links, and network interfaces), so that the communication subsystem can be clocked at a much higher frequency than a traditional conservative design (up to 1.5× increase in frequency). The NoC is designed to tolerate timing errors that arise from overclocking without substantially affecting the latency for communication. We also present a way to dynamically configure the NoC between the overclocked mode and the normal mode, where the frequency of operation is lower than or equal to the traditional design's frequency, so that the error recovery penalty is completely hidden under normal operation. Experiments on several benchmark applications show large performance improvement (up to 33% reduction in average packet latency) for the proposed system when compared to traditional systems.Index Terms-Aggressive design, networks on chip (NoCs), systems on chip (SoCs), timing errors.

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Going beyond worst-case specs with TEAtime

Cited by 46 publications

References 7 publications

An in-Situ Timing-Error Prediction and Prevention Technique for Variation-Tolerant Mac-Unit.

An in-Situ Timing-Error Prediction and Prevention Technique for Variation-Tolerant Mac-Unit.

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

Timing-Error-Tolerant Network-on-Chip Design Methodology

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