Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method

Abstract

This paper presents a method to compress partially specified test data for a given SoC in Automatic Test Equipment (ATE). A method "Hamming Distance Based 2-Dimensional Reordering with Power Efficient Don't Care Bit Filling" is presented for compression of test data in which two dimensional i.e. row and columnwise test vector reordering and power optimized don't care bit filling method is applied. The advantage of the approach is a good compression with very low test power achieved without adding area overhead. The advantages are shown by experimental results with ISCAS benchmark circuits.

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

“…As this approach uses scan frame reordering, it is not suitable to IP cores with hidden structure. The same thing is applicable to [12] which requires a large amount of area overhead to compensate the 2-D reordering. The Hamming distance-based reordering used in [13] is used as the basic scheme in this paper.…”

A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

“…Hamming distance based reordering [11] should satisfy the following two facts: ① ATPG derived test patterns contain a large amount of don't care bits [2]. ② Stuck-at faults based test patterns can be reordered without any loss of fault coverage, but the corresponding fault free outputs that are stored in ATE as golden references must be also reordered in the same sequence.…”

“…Hamming Distance is defined as the distance between two test patterns equal to the number of corresponding mismatched bits, and it is calculated by bit position wise [11] (4) don't care bit based second adjusting All rows are reordered according to the numbers of don't care bit from more to less, the row T 3 with the most don't care bit is always regarded as the new first row. T 3 : XX1X T 6 : XX00 T 7 : XX00 T 10 : XX10 T 2 : 010X T 4 : X001 T 8 : X001 T 9 : X111 T 1 : 1100 T 5 : 1110 In don't care bit based second adjusting, the location of don't care bits in each test pattern will be interchanged, and don't care bits will be changed to the front position as much as possible.…”

“…Scan-in test power dissipation is proportional to the switching activities of test pattern. In addition, other activities such as scan-in operation, scan-out operation and their transition operation between these two [11] all contribute to the number of logic state transition in test pattern and test power dissipation.…”

“…The decoder area overhead is computed as: (area of decoder*100)/(area of benchmark circuit), area of decoder includes hardware overhead of the core FSM decoder and bit swapping logic array. The proposed BIST TPG method applied with EFDR/ASFDR only requires the basic decoder, which totally avoids difference test pattern method [11]. So it neither requires any CSR nor involves any delay caused by CSR, but only needs a different routing for scan-in operation.…”