Heavy ion and proton-induced single event multiple upset

Abstract

Individual ionizing heavy ion events are shown to cause two or more adjacent memory cells to change logic states in a high density CMOS SRAM. A majority of the upsets produced by normally incident heavy ions are due to singleparticle events that causes a single cell to upset. However, for grazing angles a majority of the upsets produced by heavy-ion irradiation are due to single-particle events that cause two or more cells to change logic states.Experimental evidence of a single proton-induced spallation reaction that causes two adjacent memory cells to change logic states is presented. Results from a dual volume Monte-Carlo simulation code for proton-induced single-event multiple upsets are within a factor of three of experimental data for protons at normal incidence and 70 degrees.

Dependability assessment of by-wire control systems using fault injection

“…There are different references regarding the reality of error multiplicity on data [16], [17], [25] and [31]. Bit-flips are the consequence of such faults, and depending on the source of the fault, they appear following different patterns.…”

“…Besides the possibility of multiple incidences, high energy ions can induce multiple bit upsets if crossing through sensitive adjacent regions -either due to a single ion track or secondary particles caused by an ion collision [16] [17].…”

Multi-Bit Upset Deduction/Correction for Memory Applications

“…For the parity row we use the following formula: (6) Where is column number from 0 to 7 for eight parity bits.…”

“…The probabilities of multiple errors due to technology shrinkage have been already discussed in [4] and [5]. As the size of the memories increases the probability of having multiple bits upset increase since large number of memory cells has been discussed in [6] and [7].…”

An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories

“…This phenomenon, called multiple bit upset (MBU), can result from a high-energy particle (most likely causing double bit upsets) or a low incident angle (striking many cells in a row). 3 Experiments using proton and heavy-ion fluxes calculate the probability of a single ion provoking MBUs. [4][5][6] Error detection and correction code (EDAC) is a well-known technique for protecting storage devices against transient faults because it is implementable in a high-level design step without changes in the mask process (that is, it has low nonrecurring engineering cost).…”