Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips

Abstract

Networks-on-Chips (NoCs) are experiencing escalating susceptibility to wear-out and reduced reliability, with the risk of becoming the key point of failure in an entire multicore chip. Aiming towards seamless NoC operation in the presence of faulty communication links, in this paper we propose Hermes, a highly-robust, distributed and lightweight fault-tolerant routing algorithm, whose performance degrades gracefully with increasing faulty link counts. Hermes is a deadlockfree hybrid routing algorithm, utilizing load-balancing routing on faultfree paths to sustain high-performance, while providing pre-reconfigured escape path selection in the vicinity of faults. Additionally, Hermes identifies non-communicating network partitions in scenarios where faulty links are topologically densely distributed. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from fullsystem chip multi-processor simulations, shows that Hermes improves network throughput by up to 3× when compared against prior-art.

Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs

“…However, rerouting may introduce deadlock or livelock which can paralyze the network operations. The methods using detour can be divided into three main groups, depending on the mechanism they use to create a deadlockfree path around the fault: some approaches [1,6] opt for a more restricted set of path selection heuristics such as the turn model [2], some [3,7] use VCs, and some [1,7,8,9] require off-line reconfiguration of routing tables. Regardless of the mechanism being used, the detour-based algorithms suffer from two major drawbacks: (1) The hotspots are more likely to be created around the faults when rerouting is performed.…”

“…Reconfiguration techniques have also been widely used [9,8] to design resilient NoCs. Most of the fault-tolerant algorithms studied earlier perform route reconfiguration to bypass faults.…”

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

“…Disabled interrouter links in the network reduce connectivity. One approach to maintaining connectivity is the use of additional links in the form of escape paths [Koibuchi et al 2008;Iordanou et al 2014;Kakoee et al 2011b]. A more radical approach is to replace simple links with Quad-Function Channel buffers [DiTomaso et al 2014].…”

Twist-Routing Algorithm for Faulty Network-on-Chips

“…Recent route-reconfiguration solutions to bypass faulty links or routers can be broadly divided into two kinds, buffered solutions and deflection solutions. Buffered solutions include Ariadne [13], uDirec [12], Hermes [14], which all utilize traditional wormhole routing [15], and routing tables. Those algorithms typically take some time to update routing tables when a new fault is detected, and incur reconfiguration overhead.…”