Heterogeneous wafer-scale integration of 250nm, 300GHz InP DHBTs with a 130nm RF-CMOS technology

Abstract

The performance advantages of InP based devices over silicon devices are well known [1], [2], but the ability to fabricate complex, high transistor count ICs is limited both by the relative immaturity of the material system and a limited commercial market. Silicon based devices have made significant advances in device performance [3],[4], but have not yet matched compound semiconductor device performance.A large commercial market, however, has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both of these technologies in order to enable a new class of high performance ICs [5]. This work demonstrates the wafer scale integration of an advanced 250nm, 300GHz f T /f MAX InP DHBT technology with IBM's 130nm RF-CMOS technology (CMRF8SF). Such integration allows the rapid adoption of more advanced CMOS and InP DHBT technology generations. Process Integration:The integration process begins with a partially fabricated, full thickness, 200mm or 300mm diameter silicon CMOS wafer and a full thickness, 76.2mm or 100mm diameter InP epitaxial wafer. The CMOS wafer need only be completed to any planar metal level, and the total number of metal levels does not impact the integration process. For this demonstration, a 200mm, 6 copper metal (4 thin and 2 thick) wafer from the IBM CMRF8SF process was used. The 76.2mm InP epitaxial wafer is composed of the InP DHBT layers in an emitter up configuration [6] with the addition of a 160nm InGaAs/InP composite etch stop below the sub-collector. Shown in Figure 1, the starting InP expitaxial wafer (A) is temporarily bonded to a handle wafer (B) which allows the InP growth substrate and etch stop layers to be removed (C). A 0.5μm thick Aluminum heat spreader layer is deposited as a blanket film, and the InP DHBT layers are then permanently bonded to the CMOS wafer top surface (D). The entire 76.2mm diameter InP round can be used if the 200mm diameter CMOS wafer is cored into 76.2mm diameter rounds [5] or InP epitaxial chips can be bonded to an arbitrary diameter CMOS round [7]. For this demonstration, the 200mm IBM CMRF8SF wafer was laser cored to a 76.2mm round and the entire 76.2mm diameter InP round was used. The handle wafer is removed and standard processing techniques can then be used to fabricate the 250nm InP DHBTs [6] and the heterogeneous interconnect (E). Figure 2 shows a SEM micrograph of an InP DHBT differential pair, whose emitter area is 0.25x4.0μm 2 . Since the Heterogeneous Integration (HI) via and final interconnect have yet to be formed, the Cu interconnect level immediately below the InP DHBTs is visible. Figure 3 shows a completed InP DHBT where the final interconnect level has made contact to the emitter, base, and collector terminals of the InP DHBT. Figure 4 shows a completed 76.2mm diameter wafer.Heterogeneous Interconnects: In order to assess the yield and resistive loss of the HI via, a 1000 unit long chain of the nominal 1.0x1.0μm 2 HI via at a pitch of 5μm were elect...

The DARPA COSMOS program: The convergence of InP and Silicon CMOS technologies for high-performance mixed-signal

“…As previously mentioned, three innovative heterogeneous integration processes are currently being developed in COSMOS program: micrometer scale assembly [9], monolithic epitaxial growth [10], and epitaxial layer printing [11] approaches as illustrated in Fig. 1 A micrometer-scale assembly process is being developed by the team led by Northrop Grumman Aerospace Systems.…”

“…At the other end of the spectrum, in an approach being developed by a Raytheon-led team [10], monolithic integration methods are being explored to epitaxially grow III-Vs on CMOScompatible substrates. An intermediate approach is being studied by a team led by HRL Laboratories [11]. In order to achieve the challenging demonstration circuit performance goals, all three teams chose to integrate state-of-the-art InP HBTs with silicon CMOS transistors.…”

An Active Double-Balanced Down-Conversion Mixer in InP/Si BICMOS Operating from 70-110 GHz

“…Once bonded, the temporary handle wafer is removed and subsequent InP DHBT and heterogeneous interconnect processing starts. Additional details concerning fabrication and processing can be found in [8,9].…”

Mixed-Signal Circuits Using 250nm InP HBT Technology Integrated with 90nm CMOS

“…The basic process flow has been previously described [1,2]. A block diagram of the process flow is shown in Figure 1.…”

“…Static calibration is provided using standard CMOS current matching techniques [2] at a relatively low clock rate (10 MHz). With this approach a small device in parallel with a current source is used to adjust different current sources to match each other.…”