Hiding memory latency using fixed priority scheduling

Wasly, Saud; Pellizzoni, Rodolfo

doi:10.1109/rtas.2014.6925992

Cited by 28 publications

(19 citation statements)

References 13 publications

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“…The aim is to enable more efficient operation whereby the memory phase of one task overlaps with the execution phase of another. Yao et al (2012) presented a TDMA scheduling algorithm for PREM tasks on a multicore, and Wasly and Pellizzoni (2014) provided schedulability analysis for nonpreemptable PREM tasks on a partitioned multicore. Lampka et al (2014) proposed a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as a shared resource.…”

Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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“…A new memory-buffer chip called Centaur, which provides up to 128 MB of embedded DRAM buffer cache per processor along with an improved DRAM scheduler, was proposed in [15]. In [17], a dynamic scheduling algorithm was proposed for a set of sporadic realtime tasks that efficiently co-schedule a processor and a DMA execution to hide memory transfer latency. In [17], a dynamic scheduling algorithm was proposed for a set of sporadic realtime tasks that efficiently co-schedule a processor and a DMA execution to hide memory transfer latency.…”

Section: Previous Workmentioning

confidence: 99%

WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

Jang

2017

ETRI Journal

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State‐of‐the‐art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap‐around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap‐round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap‐around order, but the rearrangement process may increase memory latency and waste the bandwidth of on‐chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap‐around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

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“…In addition, a previous work [6] has proposed a system with DMA peripheral to overlap memory transfer with CPU computation in order to hide memory latency. A partitioned non-preemptive scheduling of cores and DMA has been introduced in [13]. Although the partitioned approach showed good results in terms of hiding access latency to main memory, the partitioned system is not always preferable as we mentioned early.…”

Section: A Memory and Cpu Co-schedulingmentioning

confidence: 99%

“…We applied the overlapping mechanism on previous work [13] for fixed-priority scheduling on a single core, albeit the work can be extended to partitioned multicore scheduling using TDMA arbitration in main memory. Although this work showed good results in terms of hiding access latency to main memory, the partitioned system is not always preferable as it requires design-time decisions to statically assign tasks to cores.…”

Section: Introductionmentioning

confidence: 99%

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Memory efficient global scheduling of real-time tasks

Alhammad

Wasly

Pellizzoni

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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Current computing architectures are commonly built with multiple cores and a single shared main memory. Even though this architecture increases the overall computation power, main memory can easily become a bottleneck. Simultaneous access to main memory from multiple cores can cause both (1) severe degradation in performance and (2) unpredictable execution time for real-time applications. We propose in this paper to mitigate these two problems by co-scheduling cores as well as the main memory for predictable execution. In particular, we use a DMA component to overlap memory with computation for hiding the memory latency and therefore increasing the system performance. The main contribution of this paper is a novel global co-scheduling algorithm along with its associated schedulability analysis for sporadic hard real-time tasks. We evaluated our system by generating synthetic tasksets based on real benchmark parameters. The results show a significant improvement in system utilization while retaining a predictable system behavior.

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Hiding memory latency using fixed priority scheduling

Cited by 28 publications

References 13 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

WARP: Memory Subsystem Effective for Wrapping Bursts of a Cache

Memory efficient global scheduling of real-time tasks

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