Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

Kanno, Yusuke; Mizuno, Hiroyuki; Yasu, Y.; Hirose, Keikichi; Shimazaki, Yasuhisa; Hoshi, T.; Miyairi, Y.; lshii, T.; Yamada, Takazo; Irita, Takahiro; Hattori, Toshihiro; Yanagisawa, K.; lrie, N.

doi:10.1109/isscc.2006.1696281

Cited by 40 publications

(17 citation statements)

References 4 publications

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“…The large power supply noise generated by such current change is a serious problem for low power digital VLSI's 15), 16) . Figure 18 shows an LSI including multiple power domains with the power gating.…”

Section: Power Supply Noise Cancellermentioning

confidence: 99%

“…The noise suppression by decreasing the package inductance and increasing the on-chip decoupling capacitance leads to the large area penalty. Conventional clock dithering 15) and power switch control 16) to slow the current change increase the wake-up time and are not useful for the frequent wake-up and power-down. To solve these problems, an on-chip noise canceller with small area penalty and the fast wake-up is proposed.…”

Section: Power Supply Noise Cancellermentioning

confidence: 99%

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Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

Takamiya

Sakurai

2009

IPSJ Transactions on System LSI Design Methodology

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In order to cope with the increasing leakage power and the increasing device variability in VLSI's, the required control size of both the space-domain and the time-domain is decreasing. This paper shows the several recent fine-grain voltage engineerings for the low power VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain power supply voltage with 3D-structured on-chip buck converters with the maximum power efficiency up to 71.3% in 0.35-µm CMOS and the fine-grain body bias control to reduce power supply voltage in 90-nm CMOS. The time-domain fine-grain voltage engineering includes accelerators for the power supply voltage hopping with a 5-ns transition time in 0.18-µm CMOS, the power supply noise canceller with the 32% power supply noise reduction in 90-nm CMOS, and backgate bias accelerators for fast wake-up with 1.5-V change of backgate voltage in 35 ns in 90-nm CMOS.

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Section: Power Supply Noise Cancellermentioning

confidence: 99%

Section: Power Supply Noise Cancellermentioning

confidence: 99%

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

Takamiya

Sakurai

2009

IPSJ Transactions on System LSI Design Methodology

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“…The challenge becomes even more significant as the diversity of modern systems increases and dynamic voltage scaling (DVS) becomes an integrated part of the power management process. Recently, hundreds of on-chip power domains with tens of different supply voltage levels have been reported, and thousand-core ICs are being considered [1][2][3][4][5][6][7]. Commercial products integrating tens of power domains with different supply voltages are already commercially available (e.g., Toshiba HD Decoding Chip with 25 power domains [6], and Samsung Exynos 4 Quad Core with 28 LDO regulators [7]).…”

Section: Introductionmentioning

confidence: 99%

Energy efficient adaptive clustering of on-chip power delivery systems

P.-Vaisband

Friedman

2015

Integration

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“…As a result, voltage level gap between the IO and core circuit is increasing. In addition, the voltage level gap in the core circuit itself is also increasing since multiple voltage domains are widely used for power reduction such as in [10][11]. Therefore, a wide-range level shift circuits for both in the IO and the core circuit are currently actively researched.…”

Section: Introductionmentioning

confidence: 99%

A 0.45V-to-2.7V inductive-coupling level shifter

Takatsu

Niitsu

Shidei

et al. 2010

2010 IEEE Asian Solid-State Circuits Conference

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This paper presents a 0.45V-to-2.7V level shifter utilizing inductive coupling. Since primary and secondary coils are AC-coupled, each coil can be biased at arbitrary voltage independent from the conversion level difference. This enables both the primary and the secondary circuits to operate at the optimal operating region. In addition, the inductive coupling itself can provide an additional intermediate level-shifting by exploiting a coil-turn ratio between the primary and the secondary coils. As a result, wide-range voltage level conversion can be achieved. Test chip measurement in 65nm CMOS demonstrates voltage level conversion from 0.45V to 2.7V. Compared to a conventional level shifter, the primary voltage is reduced by 0.24V. In addition, the energy-delay product is reduced to 1/8.

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Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

Cited by 40 publications

References 4 publications

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

Energy efficient adaptive clustering of on-chip power delivery systems

A 0.45V-to-2.7V inductive-coupling level shifter

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