High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Lin, Jason; Chiou, W.C.; Yang, Kai-Shing; Chang, Hun-Hsien; Lin, Yu‐Cheng; Liao, E.B.; Hung, Jaclyn Y.; Tsai, P.H.; Shih, Yu-Jen; Wu, Ting; Wu, Wenjing; Tsai, F.W.; Huang, Yuhui; Wang, T.Y.; Yu, Cheng‐Wei; Chang, Chih-Sheng; Chen, M.F.; Hou, S. Y.; Tung, Cheng-Huang; Jeng, Shin-Puu; Yu, Douglas

doi:10.1109/iedm.2010.5703277

Cited by 61 publications

(22 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As an example, TSV resistance as a function of thermal cycling (from -55°C/125°C) showed no detectable degradation up to 2000 cycles. Thermal cycling and thermo-mechanical issues are routinely reported in the literature [1][2] as a major problem for 3D integration and TSVs, but the 3D technology as fabricated by austriamicrosystems AG appears very robust in this regard.…”

Section: Results Of Reliability Investigationsmentioning

confidence: 98%

“…All most recently presented TSV designs use filled copper TSVs. The advantage of this approach is low TSV contact resistance, but the price that has to be paid is a high degree of mechanical stress due to the mismatch of the thermal expansion coefficient of copper and silicon [1][2]. Furthermore the depth of the TSV is limited to about 50µm, because of the limited aspect ratio that is possible for TSV etching process and the limited thickness available for copper electro plating.…”

mentioning

confidence: 99%

See 1 more Smart Citation

3D Sensor application with open through silicon via technology

Kraft

Schrank

Teva

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for More than Moore solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven open TSV technology on the basis of a 0.35m CMOS process. An application-optimized sensor-layer is processed on a specific wafer substrate, whereas the CMOS circuits of the system can remain cost-efficiently on an appropriate 0.35m CMOS or HV-CMOS technology. Another advantage of the proposed TSV solution is the geometric aspect. As the CMOS is attached to the sensor backside, almost 100% of the chip area can be used for the sensing functionality. In the presented technological approach, the sensor wafer is finalized with processing a top metal layer and successive bond oxi de layers. The bond oxide layers are planarized by chemo mechanical polishing (CMP). The CMOS wafer is fabricated using a regular 0.35m CMOS technology up to the vias before the last metal layer. A nitride layer is deposited in order to protect the integrated circuits from damages during the back grinding process. Prior to bonding, the CMOS wafer is thinned down to a thickness of 250m and then bonded to the sensor wafer by plasma activated bonding followed by an annealing step to reinforce the bond strength. TSV etching is sequentially performed in three steps: firstly, the oxide of inter-metal dielectrics is opened. Secondly, the bulk silicon of the CMOS wafer is etched using a deep reactive ion etch (DRIE) process selectively stopping on the bond oxide of the sensor wafer. After several cleaning steps the spacer oxide is deposited followed by the spacer and bond oxide etching. For TSV metallisation, Tungsten as deposited in a CVD process is chosen providing uniform conformal coating inside the op

show abstract

Section: Results Of Reliability Investigationsmentioning

confidence: 98%

mentioning

confidence: 99%

3D Sensor application with open through silicon via technology

Kraft

Schrank

Teva

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

show abstract

“…The issue of the leakage current, which could be caused by sidewall roughness, has been studied. [4,5,6] Conventional ICP and CCP plasma are difficult to optimize smooth sidewall etching and high selectivity to photo-resist for TSV fabrication.…”

Section: Introductionmentioning

confidence: 99%

A novel scallop free TSV etching method in magnetic neutral loop discharge plasma

Morikawa¹,

Murayama²,

Sakuishi³

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

View full text Add to dashboard Cite

In recent years, ''2.5D silicon interposers'' and ''Full 3D stacked'' technology for high-performance LSI has attracted much attention since this technology can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked LSI. 2.5D and 3D Si integration has great advantages over conventional two-dimensional devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing.

show abstract

“…An important part in three-dimensional integration is ThroughSilicon Via (TSV) technology [2,3]. A well-known problem in TSV reliability is the pumping phenomenon or TSV protrusion, and many studies have been made to address this issue [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Microstructure investigation of TSV copper film

Putra

Trigg

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

View full text Add to dashboard Cite

Copper Through-Silicon Via (Cu TSV) is becoming a key technology for three dimensional (3D) packaging and 3D integrated circuit (IC) applications. The microstructure of the Cu TSV is important as it not only affects the electrical properties, but may play a role in its reliability such as protrusion. In this study, physical vapor deposition (PVD) and electroplated (ECP) Cu TSV microstructure evolution with Ti and Ta barrier after thermal annealing was investigated. As deposited PVD Cu grain showed a preferred orientation on (111) and transformed into (001) after annealing. On the other hand, ECP Cu grain orientation appears to be random for both samples before and after annealing. The grain size for both PVD and ECP increased substantially after annealing at 410°C 30 min because of grain growth. However, the grain growth was more significant in Ti-barrier Cu TSV sample than the Ta-barrier one.

show abstract

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Cited by 61 publications

References 0 publications

3D Sensor application with open through silicon via technology

3D Sensor application with open through silicon via technology

A novel scallop free TSV etching method in magnetic neutral loop discharge plasma

Microstructure investigation of TSV copper film

Contact Info

Product

Resources

About