High-efficiency solar cell embedded in SOI substrate for ULP autonomous circuits

Bulteel, Olivier; Delamare, Romain; Flandre, Denis

doi:10.1109/soi.2009.5318789

Cited by 20 publications

(13 citation statements)

References 5 publications

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“…substrate are an efficient energy source for IC on the same chip, such as distributed wireless sensor networks and ultralow power (ULP) autonomous circuits that are with transparent packages [1], [2]. It can provide sole power at milliwatt level, which is an optional choice for ULP circuit design.…”

Section: S Olar Cells Integrated On Silicon-on-insulator (Soi)mentioning

confidence: 99%

Ultrathin Crystalline Silicon Heterojunction Solar Cell Integrated on Silicon-on-Insulator Substrate

Duan

Bian

et al. 2015

IEEE Trans. Electron Devices

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To achieve power generation on IC chips, a hydrogenated amorphous silicon (a-Si:H)/crystalline silicon (c-Si) heterojunction solar cell was designed and fabricated on silicon-on-insulator substrate, where a 9-µm epitaxial p-type c-Si layer served as light absorption layer and the buried SiO 2 as back surface passivation layer. It was found that a 1-µm heavily doped thin p + layer was vital for improving the cell performances. Efficiency up to 12.7% with an open-circuit voltage of 679.7 mV was achieved on a 1.0-cm 2 square cell. The device performance was also investigated by annealing at different temperatures. The results suggested that a relatively large thickness of a-Si:H and transparent conductive oxide layers could improve thermal stability of the solar cells at temperature above 300°C.Index Terms-Power generation, silicon heterojunction (SHJ) solar cell, silicon on insulator (SOI), thermal stability.

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Section: S Olar Cells Integrated On Silicon-on-insulator (Soi)mentioning

confidence: 99%

Ultrathin Crystalline Silicon Heterojunction Solar Cell Integrated on Silicon-on-Insulator Substrate

Duan

Bian

et al. 2015

IEEE Trans. Electron Devices

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“…6). The PV cell can be fabricated in the SOI substrate itself, below the SOI thin film which is used for the CMOS circuits [11]. With a PV cell of 0.5mm 2 generating 7.95µW under 100W/m 2 or 0.1 sun, the proposed charge-pump is able to provide 4.5µW at its output which corresponds to a 56.6% efficiency, the breakdown being 84.3% for the charge-pump itself and 63.1% for the clock generator while the PV cell gets biased at 95% of the Maximum Power Point (MPP).…”

Section: Ulp Rectifier and Charge-pumpmentioning

confidence: 99%

Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems

Flandre

Bulteel

Gosset

et al. 2011

2011 Faible Tension Faible Consommation (FTFC)

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In this paper, we describe applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS mixed analog-digital microsystems without compromising the functional performance. The technique is based on a pair of source-connected n-and p-MOS transistors, automatically biasing the stand-by gate-tosource voltage of the nMOSFET at a negative voltage and that of the pMOSFET at a positive level, thereby pushing the off current towards its physical limits. Playing with gate and drain connections, we have created a family of ULP basic blocks : a 2terminal diode, a 3-terminal transistor and a voltage follower. Using these blocks, we have developed a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high speed performance, highly-efficient power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.Index Terms-Ultra low leakage, Ultra low power, analog and digital CMOS circuits, logic, SRAM, power management, energy harvesting, voltage reference, SOI technology.978-1-61284-647-7/11/$26.00 ©2011 IEEE

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“…The realized chip, realized with a 0.35-µm BCD SOI [11]- [13] technology, includes 35 photovoltaic cells and an integrated circuit whose geometrical dimensions are equivalent to the ones of a single cell (Fig. 2).…”

Section: Realized Chipmentioning

confidence: 99%

Integrated self-supplied system for environmental temperature sensing

Barnabei

Grassi

Pinna

et al. 2011

2011 IEEE SENSORS Proceedings

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In this paper we present a 4-mm 2 battery-less temperature sensor, designed to collect and periodically transmit information to an ambient monitoring system. It consists of a 0.35-µm BCD SOI technology based chip including an ultra-low power integrated circuit and an energy harvesting supply unit made by 34 series-parallel connected photovoltaic cells. Each cell consists of a trench insulated p-n junction. Series connections among cells are possible because of the lack, guaranteed by the SOI insulation, of the substrate parasitic diode, typical in standard CMOS technology. The system is fully compliant with real-time applications and can work in low illumination conditions and with large variations of the photovoltaic voltage.

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High-efficiency solar cell embedded in SOI substrate for ULP autonomous circuits

Cited by 20 publications

References 5 publications

Ultrathin Crystalline Silicon Heterojunction Solar Cell Integrated on Silicon-on-Insulator Substrate

Ultrathin Crystalline Silicon Heterojunction Solar Cell Integrated on Silicon-on-Insulator Substrate

Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems

Integrated self-supplied system for environmental temperature sensing

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