High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

Lee, Junan; Park, Himchan; Song, Biao; Kim, Kiwoon; Kim, Kyunghoon; Burm, Jinwook

doi:10.1109/tcsi.2015.2451791

Cited by 39 publications

(7 citation statements)

References 22 publications

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“…The attenuation DR of the proposed VCAT in this work is larger than the others, and meanwhile, the attenuation gain can be tuned continuously while nearly all the others feature a digital controlled step attenuation characteristic except the one in the study of Padovan et al 28 However, no linearity‐in‐dB correction or improvement mechanism was adopted in their study, and the gain curve exhibits a logarithmic characteristic versus the current bias control, which implies a poor linearity‐in‐dB performance. In this work, the figure of merit is defined as

italicFOM = \frac{power}{2^{italiccontrol_italicbits} \times italicDR \times italicBW} .

…”

Section: Resultsmentioning

confidence: 99%

A large dynamic range voltage controlled attenuator with improved linearity‐in‐dB for ultrasound applications

Fei

et al. 2019

Circuit Theory & Apps

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Summary A large dynamic range (DR) and high linearity‐in‐dB voltage controlled attenuator (VCAT) for ultrasound applications was presented. Continuous tunable VCAT implemented with Metal‐Oxide‐Semiconductor (MOS) transistors used as shunt devices was proposed in this work, and the linearity‐in‐dB performance was analyzed in detail. Nonlinearity of the shunt transistors operated in different regions resulted in poor linearity‐in‐dB attenuation of the VCAT, which was undesirable in an ultrasonic receiver system. An effective linearity‐in‐dB improvement scheme was then proposed. The full scale range of the input control voltage was divided into N intervals with a same equal‐length by uniformly distributed voltage values. At these division voltages, the attenuation gains were corrected to be the ideal ones by the tracing and comparing circuits. In this way, the non‐linearity‐in‐dB was limited to the intervals between the two adjacent corrected attenuation gains, and the overall linearity of the VCAT was improved greatly. Measurement results showed that the dynamic range of the proposed attenuator was 36‐dB, and the gain errors were in a range from −1.22 to −0.55 dB. The noise figures (NF) at the commonly used ultrasonic frequencies was below 6‐dB, and the S11 was better than −10 dB over the input range of the control voltage.

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italicFOM = \frac{power}{2^{italiccontrol_italicbits} \times italicDR \times italicBW} .

…”

Section: Resultsmentioning

confidence: 99%

A large dynamic range voltage controlled attenuator with improved linearity‐in‐dB for ultrasound applications

Fei

et al. 2019

Circuit Theory & Apps

View full text Add to dashboard Cite

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“…In [1], the pixel source-follower (SF) and correlated double sampling (CDS) circuits have been optimized, achieving a continuous column readout speed of approximately 2 MHz. The column rates in [2] [3] are around 150 kHz. On the other hand, despite being a crucial component in the voltage to digital conversion, the column ADC has seldom been optimized to further improve the continuous readout speed in previous publications.…”

Section: Introductionmentioning

confidence: 99%

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

Xie

Theuwissen

2020

IEEE Trans. Circuits Syst. II

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This paper proposes a SAR ADC whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

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“…To overcome the low-speed problem, multiple two-step (TS) SS ADCs have been proposed [12][13][14][15][16][17][18][19][20][21]. A T-bit TS SS ADCs divide the A/D conversion process into M-bit coarse conversion and N-bit fine conversion where T = M＋N.…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

Zhang

Ning

et al. 2020

IEEE Access

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This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-todigital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/-0.8 LSB and the integral nonlinearity (INL) of +1.06/-0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of 7.5×775 μm 2 and the power consumption is 72 μW. INDEX TERMS Column-parallel ADC; single-slope (SS) ADC; two-step ADC; foreground calibration

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High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

Cited by 39 publications

References 22 publications

A large dynamic range voltage controlled attenuator with improved linearity‐in‐dB for ultrasound applications

A large dynamic range voltage controlled attenuator with improved linearity‐in‐dB for ultrasound applications

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

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