High hole and electron mobilities in nanocrystalline silicon thin-film transistors

Lee, Czang-Ho; Sazonov, Andrei; Nathan, Arokia

doi:10.1016/j.jnoncrysol.2005.11.149

Cited by 18 publications

(12 citation statements)

References 19 publications

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“…Using microcrystalline silicon leads then to the possibility to perform CMOS electronics at low temperature. Higher electron mobility values were obtained previously by different authors, including ourselves [4][5][6]. These values were obtained when using low temperature deposited silicon dioxide as gate insulator.…”

Section: Resultssupporting

confidence: 49%

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N and P type top‐gate microcrystalline silicon TFTs processed at low temperature (T < 200 °C) on the same glass substrate

Souleiman

Kandoussi

Belarbi

et al. 2010

Phys. Status Solidi (c)

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Low temperature deposited RF‐PECVD undoped, arsenic and boron doped μc‐Si:H films are used to fabricate the N‐type and P‐type TFTs on the same glass substrate. The transistors have a coplanar top gate configuration and a silicon nitride as gate insulator. The 50 nm thin μc‐Si:H active layer showed a thermal activation energy of the conductivity of 0.57 eV and a crystalline volume fraction of 70%. The arsenic and boron doped μc‐Si:H source/drain contact layers showed a conductivity at room temperature of 5 S/cm and 2.5 S/cm respectively. These TFTs showed a field effect mobility of 0.3 cm2/V.s for electrons and 0.2 cm2/V.s for holes and an (ION/IOFF) current ratio of 107. These results show the possibility to produce CMIS (Complementary Metal Insulator Semiconductor) inverter with silicon nitride as gate insulator at very low temperature compatible with foreign substrates such as flexible plastics or textiles. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Resultssupporting

confidence: 49%

“…Another possible way consists to use microcrystalline silicon deposited at temperature compatible with flexible substrates [3]. Some work demonstrated the feasibility of N and P-type µc-Si:H TFTs at low temperature [4][5][6]. However, these transistors have a silicon dioxide as gate insulator.…”

mentioning

confidence: 99%

N and P type top‐gate microcrystalline silicon TFTs processed at low temperature (T < 200 °C) on the same glass substrate

Souleiman

Kandoussi

Belarbi

et al. 2010

Phys. Status Solidi (c)

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“…The AIM-SPICE MOS15 a-Si:H TFT model [11] is used to simulate the electrical characteristics of ambipolar devices fabricated in [12]. Parallel n-channel and p-channel TFTs were used respectively to capture electron and hole conduction in the single device.…”

Section: Spice Modelsmentioning

confidence: 99%

SPICE simulation of nanoscale non-crystalline silicon TFTs in spiking neuron circuits

Cantley

Subramaniam

Stiegler

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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Electrical characteristics of nano-crystalline silicon (nc-Si) thin-film transistors (TFTs) are fit using SPICE device models. The corresponding device model geometry is then extrapolated down to submicron dimensions using electrical data measured on a-Si:H transistors as justification. The nanoscale devices are then used to simulate a spiking neuron circuit. The frequency of output voltage pulses in the circuit is a function of the input current. Various loads are added to the output to represent driving of many synapses. Frequency versus current curves from the circuit simulations are compared to biological models. The similarities demonstrate the feasibility of using low-temperature, large-area semiconductor materials such as nc-Si in nanoscale devices to implement neuromorphic electronic designs.

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“…This is consistent with measurements of high field-effect mobilities in transistors with architectures that place the channel at the film surface where crystallinity is highest. 2,52,53 For these reasons we focus on the structure of the film surface and the charge transport mechanisms that occur in this region.…”

Section: Microcrystalline Silicon Structurementioning

confidence: 99%

Charge transport mechanisms in organic and microcrystalline silicon field-effect transistors

et al. 2007

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Several organic and inorganic materials have emerged as promising candidates for the active layer of field-effect transistors (FETs) fabricated on flexible substrates. The charge transport models necessary for device optimization in these systems are at different stages of development. The understanding of charge transport in single-crystal and thinfilm FETs based on organic materials such as pentacene, rubrene, and other related compounds has advanced considerably in recent years and a clear picture of the relevant transport mechanisms is forming. In contrast, the theoretical description of transport in hydrogenated microcrystalline silicon (µc-Si:H) is not as well known and the published results and theories are often contradictory. We review the paradigms we feel are useful in describing the current understanding of transport in organic and µc-Si:H field-effect transistors. In the case of organic materials these include the polarization and transfer integral fluctuation model [A. Troisi and G. Orlandi, Phys. Rev. Lett. 96, 086601 (2006), J.-D. Picon et al., Phys. Rev. B 75, 235106 (2007)], the Frölich polaron model [I.N. Hulea et al., Nat. Mater. 5, 982 (2006), H. Houilli et al., J. Appl. Phys. 100, 033702 (2006)], and several trapping models [M.E. Gershenson et al., Rev. Mod. Phys. 78, 973 (2006), V. Podzorov et al., Phys Rev. Lett. 95, 226601 (2005)]. Given the heterogeneous composition and structure of microcrystalline silicon thin films, a variety of theories to describe dark conductivity have been applied to µc-Si:H including those based on percolation theory [H. Overhof et al., J. Non-Cryst. Solids 227-230, 992 (1998)], hopping models [A. Dussan and R. H. Buitrago, J. Appl. Phys. 97, 043711 (2005)], thermionic emission, and tunneling. We give a brief overview of these models and present a fluctuation-induced tunneling model that we are developing to describe charge transport in microcrystalline silicon.

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High hole and electron mobilities in nanocrystalline silicon thin-film transistors

Cited by 18 publications

References 19 publications

N and P type top‐gate microcrystalline silicon TFTs processed at low temperature (T < 200 °C) on the same glass substrate

N and P type top‐gate microcrystalline silicon TFTs processed at low temperature (T < 200 °C) on the same glass substrate

SPICE simulation of nanoscale non-crystalline silicon TFTs in spiking neuron circuits

Charge transport mechanisms in organic and microcrystalline silicon field-effect transistors

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