High performance 0.18 μm SOI CMOS technology

Leobandung, E.; Barth, E.; Sherony, M.; Lo, S.-H.; Schulz, R.; Chu, Wen Ting; Khare, Mukesh; Sadana, D. K.; Schepis, D.; Boiam, R.; Sleight, I.; White, F. R.; Assaderaghi, F.; Moy, D.; Biery, G.; Chen, T.-C.; Davari, B.; Shahidi, G.

doi:10.1109/iedm.1999.824243

Cited by 15 publications

(7 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…First used in pSeries systems, it will be staged into the iSeries at a later date. It leverages IBM technology using an 0.18-m-lithography copper and silicon-on-insulator (SOI) technology [11]. In the ongoing debate between the "speed demons" (high clock rate) and the "braniacs" (more complex design but a higher instructions-per-cycle rate [12]), IBM UNIX-based systems have traditionally been in the braniac camp.…”

Section: Introductionmentioning

confidence: 99%

POWER4 system microarchitecture

et al. 2002

View full text Add to dashboard Cite

The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems. The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form systems. In this paper we describe the processor microarchitecture as well as the interconnection architecture employed to form systems up to a 32-way symmetric multiprocessor.

show abstract

Section: Introductionmentioning

confidence: 99%

POWER4 system microarchitecture

et al. 2002

View full text Add to dashboard Cite

show abstract

“…SOI is used by several companies to improve their product characteristics [2,3]. SOI is also referenced in the 1999 international roadmap of semiconductor technologies.…”

Section: Introductionmentioning

confidence: 99%

Worst-case bias during total dose irradiation of SOI transistors

Ferlet-Cavrois

Colladant

Paillet

et al. 2000

IEEE Trans. Nucl. Sci.

124

View full text Add to dashboard Cite

show abstract

“…It is composed of 18k devices and occupies an area of 735 µm x 280 µm. The IBM CMOS8S2 SOI technology is a 0.18 µm Partially Depleted SOI CMOS process [7]. Key features include: 7 layer copper metallization with 2 reverse scaled layers to improve RC delay.…”

Section: Resultsmentioning

confidence: 99%

Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS

Nève

Flandre

Schettler

et al. 2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

View full text Add to dashboard Cite

The paper presents the design of a 64-bit carry-select adder in Branch-Based Logic, a static design style that minimizes the internal node capacitances. This feature is used to lower the dynamic power dissipation, while maintaining good speed performances. The experimental realization of the adder demonstrates an overall delay of 720 ps while only dissipating 96 mW at 1 GHz. The fabrication is based on the 0.18 µm IBM CMOS8S2 SOI technology, which uses partially depleted transistors and copper metallization.

show abstract

High performance 0.18 μm SOI CMOS technology

Cited by 15 publications

References 1 publication

POWER4 system microarchitecture

POWER4 system microarchitecture

Worst-case bias during total dose irradiation of SOI transistors

Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS

Contact Info

Product

Resources

About