High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

Sanuki, T.; Iwamoto, Toshiyuki; Ota, Ken‐ichiro; Komoda, T.; Yamazaki, Hiroshi; Eiho, A.; Miyagi, K.; Nakayama, Keiichi I.; Fuji, O.; Togo, M.; Ohno, Kazuto; Yoshimura, Hideyuki; Yoshida, Kenji; Ito, Toshihide; Minej, A.; Yoshino, Kiminori; Itani, T.; Matsuo, K.; Sato, Taichiro; Mori, S.; Nakazawa, K.; Nakazawa, M.; Shinyama, T.; Suguro, K.; Mizushima, Ichiro; Iwasa, S.; Muramatsu, S.; Nagaoka, K.; Ikeda, Masayuki; Saito, Minoru; Naruse, H.; Enomoto, Y.; Kitano, T.; Iwai, M.; Imai, K.; Nishida, Naoki; Kuwata, T.; Matsuoka, F.

doi:10.1109/iedm.2007.4418923

Cited by 8 publications

(4 citation statements)

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“…All wafers went through a shallow S/D implant and then through deposition of an additional 30-nm-thick SiO 2 layer as an antireflection layer for LA. While the wafer without α-Ge deposition may have some implant damage in the SiGe from the shallow S/D implant, significant impact on strain level is not expected following LA and rapid recrystallization [10]. The laser was operated in N 2 ambient at a wavelength of 248 nm with a pulse duration of 23 ns, with ten pulses, and a repetition rate of 1 Hz.…”

Section: Device Fabricationmentioning

confidence: 99%

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

Liu

Wong

Ang

et al. 2008

IEEE Electron Device Lett.

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We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si 0.8 Ge 0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ∼12% was achieved with this process, as compared to a strained p-FET with Si 0.8 Ge 0.2 S/D p-FETs. The I Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.Index Terms-Germanium (Ge) enrichment, laser annealing (LA), strained transistor.

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Section: Device Fabricationmentioning

confidence: 99%

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

Liu

Wong

Ang

et al. 2008

IEEE Electron Device Lett.

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“…For the continual performance improvement of 32 nm node MOSFET, stress techniques such as eSiGe [2][3][4] and stress liner [5] are indispensable. Various channel stress techniques have been proposed so far, however, eSiGe technique is the most effective stress booster for pMOSFET; accordingly, optimization of eSiGe process becomes significant for the further performance improvement.…”

Section: Introductionmentioning

confidence: 99%

A Study on aggressive proximity of embedded SiGe with comprehensive SDE engineering for 32 nm-node high-performance pMOSFET technology

Okamoto

Yasutake

Kusunoki

et al. 2008

ESSDERC 2008 - 38th European Solid-State Device Research Conference

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We have presented the high performance pMOSFET with embedded SiGe (eSiGe) technique which is applicable to 32 nm node ground rule (dense gate space) [1]. In general, close eSiGe S/D structure to the channel improves pMOSFET performance because of higher strain in the channel. However, we found the relation between boron diffusion modulation in SiGe region and short channel effect (SCE) in the context of eSiGe proximity change. Therefore, additional source drain extension (SDE) optimization is required to improve device performance with close eSiGe structure focusing on parasitic resistance reduction. As a results, we have demonstrated high drive current of 755 µA/µm at V dd = 1.0 V, I OFF = 100 nA/µm, 30 nm gate length pMOSFET.

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“…Commonly, for achieving a low resistance ultra-shallow junction, two annealing types, i.e. rapid thermal annealing (RTA) and flash lamp annealing (FLA), are employed after the S/D implant to activate the dopant and annihilate the process-induced defects [4][5][6][7][8]. The FLA benefits dopant activation more effectively, so that better shallow junctions can be achieved, but the damage recovery is not as good as traditional RTA.…”

Section: Introductionmentioning

confidence: 99%

Origins of flash lamp annealing induced p–n junction leakages in a 45 nm p-MOSFET with strained SiGe source/drain

Cheng

Fang

Hsieh

et al. 2009

J. Phys. D: Appl. Phys.

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The effects of flash lamp annealing (FLA) on source/drain (S/D) junction leakage of a 45 nm deep-submicrometre p-MOSFET with strained SiGe S/D were investigated in detail. Based on activation energy measurements, we analyse the origins of the junction leakage currents. Without FLA, the junction leakage is dominated by the trap generation current, while with FLA the leakage current is facilitated by both trap generation and band-to-band tunnelling under low and high reverse biases, respectively.

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High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

Cited by 8 publications

References 0 publications

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

A Study on aggressive proximity of embedded SiGe with comprehensive SDE engineering for 32 nm-node high-performance pMOSFET technology

Origins of flash lamp annealing induced p–n junction leakages in a 45 nm p-MOSFET with strained SiGe source/drain

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