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For the first time, we demonstrate standard cell gate density of 3650 KGate/mm 2 and SRAM cell of 0.124 μm 2 for 32nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.

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We study the level spacing distribution p(s) in the spectrum of random networks. According to our numerical results, the shape of p(s) in the Erdős-Rényi (E-R) random graph is determined by the average degree k and p(s) undergoes a dramatic change when k is varied around the critical point of the percolation transition, k = 1. When k 1, the p(s) is described by the statistics of the Gaussian orthogonal ensemble (GOE), one of the major statistical ensembles in Random Matrix Theory, whereas at k = 1 it follows the Poisson level spacing distribution. Closely above the critical point, p(s) can be described in terms of an intermediate distribution between Poisson and the GOE, the Brodydistribution. Furthermore, below the critical point p(s) can be given with the help of the regularized Gamma-function. Motivated by these results, we analyse the behaviour of p(s) in real networks such as the internet, a word association network and a protein-protein interaction network as well. When the giant component of these networks is destroyed in a node deletion process simulating the networks subjected to intentional attack, their level spacing distribution undergoes a similar transition to that of the E-R graph.

We have presented the high performance pMOSFET with embedded SiGe (eSiGe) technique which is applicable to 32 nm node ground rule (dense gate space) [1]. In general, close eSiGe S/D structure to the channel improves pMOSFET performance because of higher strain in the channel. However, we found the relation between boron diffusion modulation in SiGe region and short channel effect (SCE) in the context of eSiGe proximity change. Therefore, additional source drain extension (SDE) optimization is required to improve device performance with close eSiGe structure focusing on parasitic resistance reduction. As a results, we have demonstrated high drive current of 755 µA/µm at V dd = 1.0 V, I OFF = 100 nA/µm, 30 nm gate length pMOSFET.