High performance 600 V smart power technology based on thin layer silicon-on-insulator

Letavic, T.; Arnold, E.; Simpson, M.; Aquino, R.; Bhimnathwala, H.; Egloff, R.; Emmerik, A.; Wong, S.S.; Mukherjee, S.

doi:10.1109/ispsd.1997.601428

Cited by 55 publications

(21 citation statements)

References 9 publications

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“…7.36) [66,68]. The doping profile in the drift region is optimized such that the lateral field in the depleted drift region is uniform [66].…”

Section: (A) Soi Nldmosmentioning

confidence: 99%

“…7.36 was extended to an SOI double-RESURF LDMOS with LOCOS field gap and about 1.5-μm top silicon and 2-μm-thick BOX, implementing a dual field plate design (Fig. 7.37) [68].…”

Section: (A) Soi Nldmosmentioning

confidence: 99%

“…This combination allows a high vertical field in the BOX and a lateral field in the drift region exceeding 20 V/μm before avalanche breakdown, resulting in a low R SP of 7.6 Ω mm 2 for 600 V [68].…”

Section: (A) Soi Nldmosmentioning

confidence: 99%

“…Therefore, the doping concentration in the PLDMOS drift region must be reduced. [68] Hence, the structure is limited to 120 V for which an R SP of about 2.2 Ω mm 2 is achieved for a LOCOS drift length of about 9 μm. Other SOI PLDMOS configurations are reported that use multiple field plates [84,85] and deep-trench field plates [86,87].…”

Section: (B) Soi Pldmosmentioning

confidence: 99%

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High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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“…7.36) [66,68]. The doping profile in the drift region is optimized such that the lateral field in the depleted drift region is uniform [66].…”

Section: (A) Soi Nldmosmentioning

confidence: 99%

“…7.36 was extended to an SOI double-RESURF LDMOS with LOCOS field gap and about 1.5-μm top silicon and 2-μm-thick BOX, implementing a dual field plate design (Fig. 7.37) [68].…”

Section: (A) Soi Nldmosmentioning

confidence: 99%

Section: (A) Soi Nldmosmentioning

confidence: 99%

Section: (B) Soi Pldmosmentioning

confidence: 99%

See 2 more Smart Citations

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…There is a silicon window in the buried oxide which connects the epitaxial layer and substrate so that the breakdown voltage can be supported in the substrate. One of the revolutionary concepts in SOI power devices is the Philips linearly graded thin film technology [4] where the SOI layer is less than 0.5pim and doping concentration increases linearly from the source side to the drain side. Since the epitaxial layer is very thin, there are not enough carriers to create impact ionisation and there is also uniformity in the electric field towards the drain side due to the doping profile and these enable to support much higher breakdown voltage.…”

Section: Adopted Technologies and Device Structuresmentioning

confidence: 99%

Technology-Based Static Figure of Merit for High Voltage ICs

Iqbal

Udrea

2006

2006 International Semiconductor Conference

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This paper introduces for the first time a technology-based static figure of merit (FOM) for lateral high voltage MOSFETs (LDMOSFETs). Established figures of merit in the power semiconductor arena take into account material properties only. Here we show that the static performance of lateral power devices is very significantly influenced by the power IC technologies. Hence we develop a technology FOM that couples the breakdown voltage with the specific on-state resistance. The FOM is based on numerical simulation results and verified with the reported experimental data from different JI and SOI technologies.

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