High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

Park, H.; Rausch, W.; Utomo, H.; Matsumoto, Keīichi; Nii, H.; Kawanaka, S.; Fisher, Philip A.; Oh, Sang‐Hyun; Snare, J.; Clark, W.; Mocuta, A.; Holt, J.; Mo, R.; Sato, Tsutomu; Mocuta, D.; Lee, B.H.; Dokumaci, O.; O’Neil, P.; Brown, D.; Suenaga, Jun; Li, Y.; Brown, L. M.; Nakos, J.; Hathorn, K.; Ronsheim, P.; Kimura, Hiroshi; Doris, B.; Sudo, G.; Scheer, K.; Mittl, S.; Wagner, T.; Umebayashi, T.; Tsukamoto, Masanori; Kohyama, Y.; Cheek, J.; Yang, Inchul; Kuroda, Hideaki; Toyoshima, Y.; Pellerin, John; Schepis, D.; Agnello, P.; Welser, J.J.

doi:10.1109/iedm.2003.1269361

Cited by 9 publications

(4 citation statements)

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“…Continued drive from ever more stringent technological requirements has required incorporation of spike anneals for the device activation drive anneal. These anneals were successfully incorporated in IBM's 90 nm CMOS technologies [44].…”

Section: Improved Fm Performance Rtpolymentioning

confidence: 99%

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

Nakos

Shepard

2008

MSF

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The role of single wafer Rapid Thermal Processing (RTP) in semiconductor manufacturing has been steadily expanding over the last 2 decades. There are several reasons for the successful adaptation of this technology. These include more critical requirements by advanced semiconductor technologies with respect to thermal exposure and control, as well as tremendous improvements by the RTP equipment community in resolving some fundamental limitations of the tooling, historically restricting wide spread implementation. From rather humble beginnings, RTP technology has now established itself as indispensable to the production of advanced semiconductor products. We review the history and implementation of RTP technology in semiconductor processing technology at International Business Machines Corporation (IBM) from the late 1980s to recent time.

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Section: Improved Fm Performance Rtpolymentioning

confidence: 99%

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

Nakos

Shepard

2008

MSF

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“…Several achievements in finding new materials and developing new process for sub-100 nm device manufacturing have been made recently. These processes or materials include the elevated source/drain [29][30][31][32][33], plasma doping with flash or laser annealing [34][35][36][37][38][39][40][41][42][43], NiSi silicide [44][45][46][47][48][49][50][51][52][53][54][55][56], strained Si channel for mobility enhancement [57][58][59][60][61][62][63][64], silicon on insulator (SOI) [65][66][67], three-dimensional structure [68][69][70][71][72][73][74][75] high dielectric constant (high-k) gate insulator …”

Section: Degradation Of Performance With Downscalingmentioning

confidence: 99%

Challenges for Future Semiconductor Manufacturing

Kakushima

Wong

2006

Int. J. Hi. Spe. Ele. Syst.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

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“…Parasitic series and contact resistance will limit the performance of MUGFETs with ultra thin and tall Si fins. Combining the spacer defined fin patterning with Raised Source/Drain (S/D) by Si-SEG helps in reducing these parasitics (4)(5). In addition, an increase in the fin density can be used to merge the individual fins outside the spacer region by SEG and consequently to eliminate S/D contact pads [6].…”

Section: Introductionmentioning

confidence: 98%

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Rooyackers

Augendre

Degroote

et al. 2006

2006 International Electron Devices Meeting

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Multiple Gate Field Effect Transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction in parasitic source/drain-resistance and 3-fold increase in drive current per surface unit.

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High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

Cited by 9 publications

References 0 publications

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

The Expanding Role of Rapid Thermal Processing in CMOS Manufacturing

Challenges for Future Semiconductor Manufacturing

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

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