This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uNum (NFET, 1171 uNum dynamic) and 490 uNum (PFET, 507 d u m dynamic) at Iof levels of 100 d u m for 1.1 volt operation. The physical gate length (Lpoly) for these devices is 39 nm. The saturation currents increase to 1180 d u m and 540 d u m at Iof levels of 300 nNum, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f,,, of 193 GHz has been demonstrated along with an fT of 178 GHz.

We present enhanced 90 nm node CMOS devices on a partially depleted SO1 with 40 M I gate length, featuring advanced process modules for manufacture including RSD (Raised SourceDrain), disposable spacer, final spacer for SiD doping and silicide proximity, NiSi, and thermally optimized MOL (Middle-of-Line) process. For the first time, we systematically designed silicide proximity in SO1 and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 @/um and 420 W u m at Ioff = 40 nNum with Vdd = l.OV, for NFET and P E T , respectively), significant reduction in effective gate oxide thickness under gate inversion by -1.2 A and -2.1 A, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.

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High-resolution x-ray diffraction (HRXRD) was used to monitor silicon-on-insulator (SOI) processing steps. The use of HRXRD is attractive since it is non-destructive and can be applied directly to product wafers. We show the usefulness of this technique for the characterization of amorphizing implants for shallow junctions, solid phase re-crystallization of implanted junctions, cobalt-silicide formation, and oxidation; all are critical processes for CMOS fabrication on SOI.