High performance digital-analog mixed device on an Si substrate with resistivity beyond 1 kΩ cm

Abstract

High performance digital-analog mixed devices are fabricated on a high resistivity MCZ Si substrate with low oxygen in order to suppress a substrate noise from digital to analog circuits. The low oxygen prevents substrate resistivity reduction due to thermal donor occurred during device fabrication process. Good characteristics of digital, analog and power amplifier can be realized by optimizing process of oxynitride, halo implantation and salicide. In 0 . 1 1~ CMOS, High drivability, that is, 770 p.A/p.m for NMOS and 330 cIA/pn for PMOS was achieved at Ioff = A/w. And ff value of 90GHz for NMOS and 48 GHz for PMOS can be achieved. Additionally, high efficiency of 68% at 2 GHz operation can be realized in power amplifier with 0.30 pm gate length.

On the design of RF spiral inductors on silicon

“…Standard silicon wafer material, grown by using the Czochralski technique, is still limited to resistivities below 100 cm [31], but the recently introduced magnetic Czochralski wafers may allow for resistivities up to 1 k cm [32]. Float-zone (FZ) silicon can routinely be fabricated with resistivities up to 10 k cm [25], [28], [33], though currently only up to a 6-in wafer diameter [31]. Instead of optimizing the silicon material, there are several techniques to engineer, to replace, or to remove the silicon underneath the inductor coil.…”

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

“…Simply increasing the resistivity of the silicon substrate is the most conservative approach, and can provide for a significant improvement in isolation. The resistivity of production Czochralski (CZ) wafers is currently limited to a maximum of roughly 10-20 cm, although a new technique known as Magnetic Czochralski (MCZ) has demonstrated resistivities up to 1 k cm [7]. In addition, Float-Zone (FZ) silicon wafers can achieve resistivities of up to 10 k cm, although the cost of FZ material is currently substantially higher than that of CZ wafers [8].…”

Physics and compact modeling of SOI substrates with buried ground plane (GPSOI) for substrate noise suppression

“…Substrate crosstalk can be reduced by manufacturing a substrate with inherent crosstalk suppression capabilities including the use of high resistivity substrates (i.e. 200 R-cm resistivity) [2], [ 6 ] . Structures such as guard rings and dielectric trenches can also be utilized alone or in combination with high,resistivity substrates.…”