High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Hsieh, Dong‐Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien−Sheng

doi:10.1109/ted.2016.2611021

Cited by 13 publications

(3 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Importantly, the on-state current (I ON ) of 318 μA μm -1 , which was normalized by W eff =58 nm (i.e. W eff =2×W NS +2×T NS ) was obtained at V GS − V T,sat =1 V and V DS =1 V, indicating that I ON in our device shows higher drive current values compared to previously reported GAA silicon nanowire MOSFETs due to enlarged W eff without sacrificing the other performance aspects [4,[16][17][18]. In addition, the certain kink effect was not observed in the output characteristics, which confirms that the devices were fully depleted, and there are no sharp corners on the SiNS owing to the sacrificial oxidation during the processes.…”

Section: Measurement Results and Discussionmentioning

confidence: 62%

Design study of the gate-all-around silicon nanosheet MOSFETs

Lee

Park

Choi

et al. 2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

The gate-all-around (GAA) silicon nanosheet (SiNS) metal-oxide-semiconductor field-effect transistor (MOSFET) structures have been recognized as excellent candidates to achieve improved power performance and area scaling compared to the current FinFET technologies. Specifically, SiNS structures provide high drive currents due to wide effective channel width (W eff ) while maintaining short-channel control. In this paper, we fabricate a GAA SiNS MOSFET fully surrounded by a gate with a gate length (L G ) of 22 nm, a SiNS width (W NS ) of 23 nm, and SiNS thickness (T NS ) of 6 nm. In addition, the fabricated GAA SiNS MOSFETs were evaluated for electrostatic characteristics and short-channel effects (SCEs) according to various channel length and width dimensions. We confirmed that the GAA SiNS MOSFET showed similar short-channel controllability regardless of W NS due to the extremely thin T NS . In addition, we analyzed SCEs of GAA SiNS MOSFETs with different T NS through simulation.

show abstract

Section: Measurement Results and Discussionmentioning

confidence: 62%

Design study of the gate-all-around silicon nanosheet MOSFETs

Lee

Park

Choi

et al. 2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…This means that dopant activation is not required, unlike in MOSFETs. JLFETs are advantageous for scale-down, surface mobility degradation, and short-channel effects [ 18 ]. A new circuit simulation model has been proposed in which the M3DIC composed of MOSFETs (M3DIC-MOSFETs) reflect direct current (DC)/alternating current (AC) and transient inter-layer electrical coupling [ 19 ].…”

Section: Introductionmentioning

confidence: 99%

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Ahn

2020

Micromachines

View full text Add to dashboard Cite

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

show abstract

“…Currently, numerous JLFET structures they have proposed utilising poly silicon as the channel material. 50,51 To achieve extreme gate controllability in the aforementioned JL FETs, the channel thickness (T ch ) was reduced (3 nm) to effectively turn OFF devices. Nonetheless, it suggests that the series resistances and carrier mobility of these devices will increase and decrease, respectively, in order to further affect device performance.…”

mentioning

confidence: 99%

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Raut¹,

Nanda²,

Panda³

2023

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Junction-less field effect transistors, also known as JLFETs, are widely regarded as the most promising candidate to replace the conventional metal oxide semiconductor field effect transistors (MOSFETs) currently used in integrated circuit technology. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold slope and drain induced barrier lowering (DIBL). Due to its gate coupling, the gate-all-around (GAA) JLFET is a better contender to uphold Moore's law than other existing device architectures and regular JLFET, allowing more precise channel tuning. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, no comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters have been provided in a single resource. From device evaluation and application to qualitative and quantitative parameter analysis studies likewise subthreshold swing, DIBL and switching ratio, this review provides comprehensive information on the various structures of Junctionless and GAA JLFETs. Furthermore, various device modeling techniques of JLFETs for enhancing the device's characteristics and its application in various semiconductor industries are provided.

show abstract

High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Cited by 13 publications

References 33 publications

Design study of the gate-all-around silicon nanosheet MOSFETs

Design study of the gate-all-around silicon nanosheet MOSFETs

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Review—Recent Trends on Junction-Less Field Effect Transistors in Terms of Device Topology, Modeling, and Application

Contact Info

Product

Resources

About