High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

Lin, Chun‐Jung; Tsui, Bing‐Yue; Yang, Ming-Jui; Huang, Ruei-Hao; Chien, Chao–Hsin

doi:10.1109/led.2006.872832

Cited by 68 publications

(24 citation statements)

References 17 publications

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“…Thin film transistors based on amorphous oxide films (OxTFTs) have attracted tremendous interest as TFT backplanes in active-matrix organic light emitting diodes (OLEDs) and liquid crystal displays owing to their high mobilities. [1][2][3][4][5][6][7] Intensive developments on oxide compounds including InO x -based, [8][9][10][11][12][13] ZnO x -based, 14 SnO x -based 15 and mixed channel materials such as InZnO x -based OxTFTs [16][17][18][19][20][21][22][23][24][25] have been widely studied in OxTFTs in recent decades because of their excellent electrical stabilities and high mobilities. Among them, InGaZnO (IGZO) 1,2,26 and InSnZnO (ITZO) 18,19 are currently being developed for use as commercial TFT backplanes because of their superior properties and high electron mobilities.…”

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confidence: 99%

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

et al. 2015

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The stable operation of transistors under a positive bias stress (PBS) is achieved using Hf incorporated into InOx-based thin films processed at relatively low temperatures (150 to 250 °C). The mobilities of the Hf-InOx thin-film transistors (TFTs) are higher than 8 cm2/Vs. The TFTs not only have negligible degradation in the mobility and a small shift in the threshold voltage under PBS for 60 h, but they are also thermally stable at 85 °C in air, without the need for a passivation layer. The Hf-InOx TFT can be stable even annealed at 150 °C for positive bias temperature stability (PBTS). A higher stability is achieved by annealing the TFTs at 250 °C, originating from a reduction in the trap density at the Hf-InOx/gate insulator interface. The knowledge obtained here will aid in the realization of stable TFTs processed at low temperatures.

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confidence: 99%

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

et al. 2015

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“…The important device parameters of Eu 2 O 3 dielectric incorporated LTPS-TFTs are listed in Table I. An improvement in device performance is observed compared with other recently published works with different gate dielectrics including SiO 2 , 15 Y 2 O 3 , 16 HfO 2 , 17 and Pr 2 O 3 . 18 The Eu 2 O 3 LTPS-TFT can speedily fill the trap states at the grain boundary and fast turn on the device due to the ultra thin EOT and large gate capacitance density.…”

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confidence: 75%

Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu2O3 gate dielectrics

Yen

Chiang

et al. 2012

Applied Physics Letters

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In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu 2 O 3 gate dielectric. High-j Eu 2 O 3 LTPS-TFT annealed at 500 C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm 2 /V-s, a small subthreshold swing of 142 mV/decade, and a high I on /I off current ratio of 1.34 Â 10 7. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu 2 O 3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu 2 O 3 LTPS-TFT device. V

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“…were developed and a steep SS was successfully realized, reaching up to 60 mV/dec (Fig. 6)666768697071. However, a larger dielectric constant is needed to reach 60 mV/dec.…”

Section: Resultsmentioning

confidence: 99%

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Park

Jang

Kim

et al. 2016

Sci Rep

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Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm2/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.

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High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

Cited by 68 publications

References 17 publications

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu2O3 gate dielectrics

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

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