In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu 2 O 3 gate dielectric. High-j Eu 2 O 3 LTPS-TFT annealed at 500 C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm 2 /V-s, a small subthreshold swing of 142 mV/decade, and a high I on /I off current ratio of 1.34 Â 10 7. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu 2 O 3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu 2 O 3 LTPS-TFT device. V

We developed a high-k HoTiO3 gate dielectric deposited on Si (100) through reactive cosputtering. They found that the HoTiO3 dielectrics annealed at 800oC exhibited excellent electrical properties such as high capacitance value, small density of interface state, almost no hysteresis voltage, and low leakage current. This phenomenon is attributed to the decrease in intrinsic defect due to the formation of well-crystallized HoTiO3 structure and composition.

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