High Speed Digital Image Correlation for Transient-Shock Reliability of Electronics

Lall, Pradeep; Panchagade, Dhananjay; Iyengar, D.; Shantaram, Sandeep; Suhling, Jeff; Schrier, H.

doi:10.1109/ectc.2007.373908

Cited by 53 publications

(8 citation statements)

References 34 publications

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“…Based on this, we conducted a simple experiment in which we drop-tested a bare FR-4 board, and measuring the board deflection with a high-speed digital camera at 30,000 frames per second, validated our assumption. We measured a damping ratio by performing digital image correlation [11] on several points on the surface of the board. By analyzing the deflection of the board, we calculated a damping ratio of 0.0029 associated with the fundamental vibration mode of the board.…”

Section: Finite Element Modelingmentioning

confidence: 99%

Characterization of drop impact survivability of a 3D CSP stack module

Peterson

Chen

Karulkar

2008

2008 58th Electronic Components and Technology Conference

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Chip scale packages (CSPs) are widely used in miniaturized electronic systems, and the performance advantages and reliability of single layer packages have been well studied for consumer applications. Three dimensional stacked modules allow for further miniaturization while retaining manufacturability and performance advantages, but they are not yet as widely used or investigated as single layer packages. Of particular concern is the survivability of a board mounted, stacked module under board level drop impact and shock loading, which may soon be of great importance in consumer, industrial and military applications. A CSP stack module is fabricated by stacking several CSPs to achieve high-density 3D systems without increasing the package's footprint. But it also introduces more probabilities of mechanical failure including drop impact-induced malfunction in solder interconnections. In order to evaluate the survivability of a stacked package, we have developed a model for a two level CSP stack module attached to a FR-4 board following the JEDEC standard. With this assembly undergoing drop impact in the 0º orientation (horizontal drop) under two types of impulse loads, we discuss the results of board-level impacts theoretically and numerically. Our results suggest that (1) the solder balls at the first CSP level are the determining factor in package reliability, (2) the first CSP level is most susceptible to damage and failure for the horizontal drop, and (3) damages in the higher level solder joints are due to a combination of vibration induced and stress wave induced stresses.

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Section: Finite Element Modelingmentioning

confidence: 99%

Characterization of drop impact survivability of a 3D CSP stack module

Peterson

Chen

Karulkar

2008

2008 58th Electronic Components and Technology Conference

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“…Feature vectors have been developed based on mahalanobis distance, wavelet packet energy decomposition [Lall 2006 a,b ], joint time-frequency analysis in the timefrequency window [Lall 2007 a,b ], and autoregressive moving average based on time and spectral domain feature vectors [Lall 2008], KL transform [Lall 2009], and self organized mapping [Lall 2010]. …”

Section: Introductionmentioning

confidence: 99%

Identification of failure modes in portable electronics subjected to mechanical-shock using supervised learning of damage progression

Lall

Gupta

Goebel

2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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An anomaly detection and failure mode classification method has been developed for electronic assemblies with multiple failure modes. The presented prognostic health management method targets the pre-failure space of the electronic assembly life to trigger repair or replacement of impending failures. Presently, health monitoring systems focus on reactive diagnostic detection of failure modes. Examples of diagnostic detection include the built in self test and on-board diagnostics. In this paper, damage pre-cursors from timespectral measurements of the electronic assemblies has been measured under applied vibration and shock stimulus. The time-evolution of spectral content of the damage pre-cursors has been studied using joint time frequency analysis in a fullfield manner on the printed circuit assembly. Frequency moments have been used to build a feature vector. Evolution of the feature vector with damage initiation and progression has been studied under shock and vibration. The feature vector from multiple locations in the board assemblies has been mapped into a de-correlated feature space using Sammon's mapping. Several chip-scale packages have been studied, with SAC305 and SAC405 leadfree second-level interconnects. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification.In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. The neural net has been trained using simulated data-sets created from error-seeded models with specific failure modes. The neural net has then been used to identify and classify the failure modes in board assemblies experimentally. Supervised learning of multilayer neural net in conjunction with parity has been used to identify the hardseparation boundaries between failure mode clusters in the de-correlated feature space. The assemblies have been crosssectioned to verify the identified failure modes. Crosssections indicate that the experimentally measured failures modes correlate well with the position of the cluster in the decorrelated feature space. IntroductionElectronics in avionics, military, defense, automobile, implantable medical applications experience harsh environments of mechanical shock and vibration for extended

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Section: Introductionmentioning

confidence: 99%

Self-organized mapping of failure modes in portable electronics subjected to drop and shock

Lall

Gupta

Panchagade

2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Portable electronic products subjected to transient shock may exhibit multiple failure modes in vicinity of the interconnects. Failure is often diagnosed by loss of functionality using techniques including the built-in self test, which provides limited insight into reliability and remaining useful life. In this paper prognostic framework for electronic systems has been developed with neural network based self organizing maps. The presented approach resides in the pre-failure space with a focus on electronic systems with multiple failure modes. Unsupervised learning of the neural net has been used to train the neural net for identification of individual failure modes. Feature vectors have been developed based on damage pre-cursors from time-spectral measurements. The clustered damage pre-cursors have been correlated with failure modes of the underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC305, SAC405 alloys.

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High Speed Digital Image Correlation for Transient-Shock Reliability of Electronics

Cited by 53 publications

References 34 publications

Characterization of drop impact survivability of a 3D CSP stack module

Characterization of drop impact survivability of a 3D CSP stack module

Identification of failure modes in portable electronics subjected to mechanical-shock using supervised learning of damage progression

Self-organized mapping of failure modes in portable electronics subjected to drop and shock

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