High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS

Addressing link-level design tradeoffs for integrated photonic interconnects

“…However, a large optical power is required to create the rail-to-rail voltage swing at the PD. As shown in Section II-B, differential TIAs can be used to amplify the signal at the cost of added noise and circuit power [16] [19].…”

Extracting Analytical Nonlinear Models from Analog Circuits by Recursive Vector Fitting of Transfer Function Trajectories

“…The bandwidth of the buffer equals 3GHz and the DC-gain equals 2. The buffer is implemented as a chain of 4 differential amplifiers using 27 transistors and was processed in the UMC 0.13µm CMOS technology [11]. As the buffer drives large signal inputs,…”

A fully-integrated 125-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

“…As one of these, low-cost 850-nm optical interconnects based on vertical-cavity surface-emitting lasers and multimode fibers are finding increasing ranges of applications such as home networks [6], communications in vehicles and airplanes [7], rack-to-rack interconnects within data centers and computer clusters [8], [9], and onboard interconnects [8][9][10][11][12][13]. 850-nm optical receivers that include monolithically integrated silicon photodetectors (PDs) and complementary metal-oxide-semiconductor (CMOS) electronics are particularly attractive since they have great cost benefits provided by CMOS technology as well as improved performance due to elimination of parasitic pad capacitances and bonding wire inductances that are unavoidable in hybrid approaches [14][15][16][17][18][19][20].…”

“…Several integrated optical receivers based on standard CMOS technology (CMOS-Rxs) have been reported [14][15][16][17][18][19][20][21]. The most critical issue for realizing high-performance CMOSRxs is development of high-performance CMOS-compatible silicon photodetectors (CMOSPDs).…”